Change in coreboot[master]: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10

[Reka Norman (Code Review)]

Attention is currently required from: Reka Norman.
Hello Reka Norman,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/62585

to review the following change.

Change subject: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10
......................................................................

mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10

When using CNVi wifi on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe wifi.

BUG=b:222595137
TEST=Bluetooth works on nivviks

Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman 
---
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
M src/mainboard/google/brya/variants/nereid/overridetree.cb
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
3 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/62585/1

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 91c633a..d85e230 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -25,7 +25,6 @@
    register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB2_A0
    register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# USB2_A1
    register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A0
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port A1
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index add5e21..ab714c8 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -13,6 +13,7 @@
    register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WFC
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# BT port for PCIe WLAN

device domain 0 on
    	device ref i2c1 on
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index 194b26f..93fe1b6 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -12,6 +12,8 @@
    register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
    register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT port for CNVi WLAN
+
    device domain 0 on
    	device ref ipu on
    		chip drivers/intel/mipi_camera
@@ -300,7 +302,7 @@
    					register "type" = "UPC_TYPE_INTERNAL"
    					register "reset_gpio" =
    						"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
-						device ref usb2_port8 on end
+						device ref usb2_port10 on end
    				end
    				chip drivers/usb/acpi
    					register "desc" = ""USB3 Type-A Port A0 (MLB)""