[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR

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Attention is currently required from: Angel Pons, Felix Held.

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Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
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Patch Set 5:

(1 comment)

File src/soc/intel/common/block/itss/itss.c:

https://review.coreboot.org/c/coreboot/+/85012/comment/a53d2756_13e971b1?usp... :
PS5, Line 138: enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin)
> Where is this function used?

This function is used to return which PIRQ a device INT pin is routed to. In https://review.coreboot.org/c/coreboot/+/85013, I improved `intel_write_pci_PRT()` so that it could write _PRT method for other domains. To use that function, SoC should read ITSS PCI Interrupt Route (PIR) registers to get connections between INT pin and PIRQ.