[S] Change in coreboot[main]: sb/intel/common/spi: Fix I/O alignment

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Kyösti Mälkki, Patrick Rudolph, Paul Menzel.

Hello Angel Pons, Kyösti Mälkki, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78090?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Code-Review+1 by Paul Menzel, Code-Review+2 by Angel Pons, Code-Review+2 by Kyösti Mälkki, Verified+1 by build bot (Jenkins)

Change subject: sb/intel/common/spi: Fix I/O alignment
......................................................................

sb/intel/common/spi: Fix I/O alignment

On ICH9 the SPI control register is not naturally aligned
and a word write might be split into smaller naturally aligned
I/O transactions.

As the first byte starts a new SPI transfer, replace the existing
word write with two byte writes and write the second byte first.

This is required for platforms that do not support unaligned
word I/O instructions and would start a SPI transfer while the
second byte hasn't reached the control register yet.

TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer
      early.

Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/common/spi.c
1 file changed, 16 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/78090/2