Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48897 )
Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ......................................................................
*/Makefile.inc: Add some INTERMEDIATE targets to .PHONY
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M payloads/external/Makefile.inc M src/cpu/intel/fit/Makefile.inc M src/security/intel/cbnt/Makefile.inc M src/security/intel/txt/Makefile.inc M src/soc/intel/common/block/fast_spi/Makefile.inc M src/southbridge/intel/common/firmware/Makefile.inc 6 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/48897/1
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 823cd87..119b4dd 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,6 +102,7 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) ifneq ($(CONFIG_UPDATE_IMAGE),y) +PHONY+=seabios_ps2_timeout INTERMEDIATE+=seabios_ps2_timeout seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" @@ -111,6 +112,7 @@ endif
ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +PHONY+=seabios_sercon INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" @@ -118,6 +120,7 @@ endif
ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +PHONY+=seabios_thread_optionroms INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 9866684..20483d8 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -6,6 +6,7 @@
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
+PHONY+=add_mcu_fit INTERMEDIATE+=add_mcu_fit add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Microcode\n" @@ -14,6 +15,7 @@ # Second FIT in TOP_SWAP bootblock ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+PHONY+=add_ts_mcu_fit INTERMEDIATE+=add_ts_mcu_fit add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Top Swap: Microcode\n" diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 2f0c510..046f860 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -9,6 +9,7 @@ boot_policy_manifest.bin-type := raw boot_policy_manifest.bin-align := 0x10
+PHONY+=add_bpm_fit INTERMEDIATE+=add_bpm_fit add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -20,6 +21,7 @@ key_manifest.bin-type := raw key_manifest.bin-align := 0x10
+PHONY+=add_km_fit INTERMEDIATE+=add_km_fit add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 77a5f69..dee4949 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -28,6 +28,7 @@
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
+PHONY+=add_acm_fit INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ @@ -42,6 +43,7 @@
ibb-files += bootblock
+PHONY+=add_ibb_fit INTERMEDIATE+=add_ibb_fit add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index 79a2f97..d99c44f 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -46,6 +46,7 @@ done; \ if [ $$fail -eq 1 ]; then false; fi
+PHONY+=check-fmap-16mib-crossing INTERMEDIATE+=check-fmap-16mib-crossing
CBFSTOOL_ADD_CMD_OPTIONS += --ext-win-base $(CONFIG_EXT_BIOS_WIN_BASE) --ext-win-size $(CONFIG_EXT_BIOS_WIN_SIZE) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 516cd4d..cc0a318 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -7,6 +7,7 @@ # image outside of CBFS
ifeq ($(CONFIG_HAVE_IFD_BIN),y) +PHONY+=add_intel_firmware INTERMEDIATE+=add_intel_firmware else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) files_added:: warn_intel_firmware
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48897 )
Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ......................................................................
Patch Set 2: Code-Review+1
What problem does this solve? I read https://www.gnu.org/software/make/manual/html_node/Special-Targets.html and https://www.gnu.org/software/make/manual/html_node/Phony-Targets.html#Phony-... and https://www.gnu.org/software/make/manual/html_node/Chained-Rules.html#Chaine...
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48897 )
Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+1
What problem does this solve? I read https://www.gnu.org/software/make/manual/html_node/Special-Targets.html and https://www.gnu.org/software/make/manual/html_node/Phony-Targets.html#Phony-... and https://www.gnu.org/software/make/manual/html_node/Chained-Rules.html#Chaine...
In Makefiles a target should be .PHONY if the target is not a real file.
For instance if someone adds a file named 'clean'. 'make clean' won't do anything anymore as clean already exists. To avoid this the target can be added to the .PHONY target.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48897 )
Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48897 )
Change subject: */Makefile.inc: Add some INTERMEDIATE targets to .PHONY ......................................................................
*/Makefile.inc: Add some INTERMEDIATE targets to .PHONY
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897 Reviewed-by: Idwer Vollering vidwer@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M payloads/external/Makefile.inc M src/cpu/intel/fit/Makefile.inc M src/security/intel/cbnt/Makefile.inc M src/security/intel/txt/Makefile.inc M src/soc/intel/common/block/fast_spi/Makefile.inc M src/southbridge/intel/common/firmware/Makefile.inc 6 files changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Idwer Vollering: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 3a40e5d..6fde12f 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,6 +102,7 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) ifneq ($(CONFIG_UPDATE_IMAGE),y) +PHONY+=seabios_ps2_timeout INTERMEDIATE+=seabios_ps2_timeout seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" @@ -111,6 +112,7 @@ endif
ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +PHONY+=seabios_sercon INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" @@ -118,6 +120,7 @@ endif
ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +PHONY+=seabios_thread_optionroms INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 9866684..20483d8 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -6,6 +6,7 @@
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
+PHONY+=add_mcu_fit INTERMEDIATE+=add_mcu_fit add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Microcode\n" @@ -14,6 +15,7 @@ # Second FIT in TOP_SWAP bootblock ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+PHONY+=add_ts_mcu_fit INTERMEDIATE+=add_ts_mcu_fit add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) @printf " UPDATE-FIT Top Swap: Microcode\n" diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index f2e5c76..349d3a9 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -6,6 +6,7 @@ boot_policy_manifest.bin-type := raw boot_policy_manifest.bin-align := 0x10
+PHONY+=add_bpm_fit INTERMEDIATE+=add_bpm_fit add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -17,6 +18,7 @@ key_manifest.bin-type := raw key_manifest.bin-align := 0x10
+PHONY+=add_km_fit INTERMEDIATE+=add_km_fit add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 77a5f69..dee4949 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -28,6 +28,7 @@
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
+PHONY+=add_acm_fit INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ @@ -42,6 +43,7 @@
ibb-files += bootblock
+PHONY+=add_ibb_fit INTERMEDIATE+=add_ibb_fit add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index 79a2f97..d99c44f 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -46,6 +46,7 @@ done; \ if [ $$fail -eq 1 ]; then false; fi
+PHONY+=check-fmap-16mib-crossing INTERMEDIATE+=check-fmap-16mib-crossing
CBFSTOOL_ADD_CMD_OPTIONS += --ext-win-base $(CONFIG_EXT_BIOS_WIN_BASE) --ext-win-size $(CONFIG_EXT_BIOS_WIN_SIZE) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 588c663..a542d7e 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -7,6 +7,7 @@ # image outside of CBFS
ifeq ($(CONFIG_HAVE_IFD_BIN),y) +PHONY+=add_intel_firmware INTERMEDIATE+=add_intel_firmware else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) files_added:: warn_intel_firmware
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Idwer Vollering (Code Review)
-
Patrick Georgi (Code Review)