Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63393 )
Change subject: nb/intel/gm45: Don't use __SIMPLE_DEVICE__ ......................................................................
nb/intel/gm45: Don't use __SIMPLE_DEVICE__
Change-Id: I27445f39d9ce9c995606229903a10d8c81c0ddb2 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/romstage.c M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/early_init.c 10 files changed, 46 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63393/1
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3f632a1..f5ea1f5 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -12,6 +12,7 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF + select NO_EARLY_SIMPLE_DEVICE
config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e911064..ee8b0f2 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -6,7 +6,7 @@
void gm45_early_init(void) { - const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); + const struct device *d0f0 = __pci_0_00_0;
/* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d610f31..bb067d4 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -203,7 +203,7 @@ /* * Graphics frequencies */ -#define GCFGC_PCIDEV PCI_DEV(0, 2, 0) +#define GCFGC_PCIDEV __pci_0_02_0 #define GCFGC_OFFSET 0xf0 #define GCFGC_CR_SHIFT 0 #define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 7b0b1e5..bd7e391 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -15,9 +15,9 @@ /* The PEG settings have to be set before ASPM is setup on DMI. */ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); - const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); - const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0); + const struct device * mch_dev = __pci_0_00_0; + const struct device * peg_dev = __pci_0_01_0; + const struct device * igd_dev = __pci_0_02_0;
printk(BIOS_DEBUG, "Enabling IGD.\n");
@@ -77,7 +77,7 @@
static void disable_igd(const sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0);
printk(BIOS_DEBUG, "Disabling IGD.\n");
@@ -98,7 +98,7 @@
void init_igd(const sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0);
const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) @@ -109,7 +109,7 @@
void igd_compute_ggc(sysinfo_t *const sysinfo) { - const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const struct device * mch_dev = PCI_DEV(0, 0, 0);
const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8b..54f2de1 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -11,8 +11,8 @@ void init_iommu(void) { /* FIXME: proper test? */ - int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; - int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); + int me_active = pci_read_config8(__pci_0_03_0, PCI_CLASS_REVISION) != 0xff; + int stepping = pci_read_config8(__pci_0_00_0, PCI_CLASS_REVISION);
mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */ if (stepping != STEPPING_B2) { @@ -31,9 +31,9 @@ mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */
/* clear GTT */ - u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); + u16 gtt = pci_read_config16(__pci_0_00_0, D0F0_GGC); if (gtt & 0x400) { /* VT mode */ - const pci_devfn_t igd = PCI_DEV(0, 2, 0); + const struct device * igd = __pci_0_02_0;
/* setup somewhere */ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); @@ -49,7 +49,7 @@
if (stepping == STEPPING_B3) { mchbar_setbits8(0xffc, 1 << 4); - const pci_devfn_t peg = PCI_DEV(0, 1, 0); + const struct device * peg = __pci_0_01_0;
/* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 295bf5b..c9c292f 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -93,8 +93,8 @@ const int sdvo_enabled, const int peg_x16) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); - const pci_devfn_t pciex = PCI_DEV(0, 1, 0); + const struct device *mch = __pci_0_00_0; + const struct device *pciex = __pci_0_01_0;
printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, peg_enabled?"enabled":"disabled", @@ -136,7 +136,7 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) { u32 tmp32; - const pci_devfn_t pciex = PCI_DEV(0, 1, 0); + const struct device *pciex = __pci_0_01_0;
/* Prerequisites for ASPM: */ if (peg_enabled) { @@ -221,7 +221,7 @@ /* Exit latencies should be checked to be supported by the endpoint (ICH), but ICH doesn't give any limits. */
- if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) + if (LPC_IS_MOBILE(__pci_0_1f_0)) dmibar_setbits8(DMILCTL, 3 << 0); // enable ASPM L0s, L1 (write-once) else dmibar_setbits8(DMILCTL, 1 << 0); // enable ASPM L0s (write-once) @@ -271,7 +271,7 @@
void gm45_late_init(const stepping_t stepping) { - const pci_devfn_t mch = PCI_DEV(0, 0, 0); + const struct device * mch = __pci_0_00_0; const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = mchbar_read16(0x40) >> 8 & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 35d71c0..e6f0e82 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -30,7 +30,7 @@
void get_gmch_info(sysinfo_t *sysinfo) { - sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); + sysinfo->stepping = pci_read_config8(__pci_0_00_0, PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && (sysinfo->stepping != STEPPING_CONVERSION_A1)) die("Unknown stepping.\n"); @@ -43,12 +43,12 @@ sysinfo->cores = ((eax >> 26) & 0x3f) + 1; printk(BIOS_SPEW, "%d CPU cores\n", sysinfo->cores);
- u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_CAPID0+8); + u32 capid = pci_read_config16(__pci_0_00_0, D0F0_CAPID0+8); if (!(capid & (1<<(79-64)))) { printk(BIOS_SPEW, "iTPM enabled\n"); }
- capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0+4); + capid = pci_read_config32(__pci_0_00_0, D0F0_CAPID0+4); if (!(capid & (1<<(57-32)))) { printk(BIOS_SPEW, "ME enabled\n"); } @@ -142,7 +142,7 @@ printk(BIOS_SPEW, "PCIe-to-GMCH enabled\n"); }
- capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0); + capid = pci_read_config32(__pci_0_00_0, D0F0_CAPID0);
u32 ddr_cap = capid>>30 & 0x3; switch (ddr_cap) { @@ -191,7 +191,7 @@ void enter_raminit_or_reset(void) { /* Interrupted RAM init or inconsistent system? */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + u8 reg8 = pci_read_config8(__pci_0_1f_0, 0xa2);
if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ /* Ignore S4-assertion-width violation like original BIOS. */ @@ -201,18 +201,18 @@
if (reg8 & (1 << 7)) { /* interrupted RAM init */ /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); + reg8 = pci_read_config8(__pci_0_1f_0, 0xa4); + pci_write_config8(__pci_0_1f_0, 0xa4, reg8 | 0x08); */
/* Clear bit7. */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~(1 << 7)); + pci_write_config8(__pci_0_1f_0, 0xa2, reg8 & ~(1 << 7));
printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); gm45_early_reset(); } /* Mark system to be in RAM init. */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); + pci_write_config8(__pci_0_1f_0, 0xa2, reg8 | (1 << 7)); }
/* For a detected DIMM, test the value of an SPD byte to @@ -1225,17 +1225,17 @@ } /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_update_config8(__pci_0_00_0, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); uma_sizem += 2; }
const unsigned int mmio_size = get_mmio_size(); const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem; - const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; + const int me_active = pci_read_config8(__pci_0_03_0, PCI_CLASS_REVISION) != 0xff; const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; const unsigned int claimCapable = - !(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0 + 4) & (1 << (47 - 32))); + !(pci_read_config32(__pci_0_00_0, D0F0_CAPID0 + 4) & (1 << (47 - 32)));
const unsigned int TOM = total_mb[0] + total_mb[1]; unsigned int TOMminusME = TOM - usedMEsize; @@ -1260,11 +1260,11 @@ REMAPlimit -= 64; }
- pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, (TOM >> 7) & 0x1ff); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, TOLUD << 4); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, TOUUD); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); + pci_write_config16(__pci_0_00_0, D0F0_TOM, (TOM >> 7) & 0x1ff); + pci_write_config16(__pci_0_00_0, D0F0_TOLUD, TOLUD << 4); + pci_write_config16(__pci_0_00_0, D0F0_TOUUD, TOUUD); + pci_write_config16(__pci_0_00_0, D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); + pci_write_config16(__pci_0_00_0, D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff);
/* Program channel mode. */ switch (mode) { @@ -1553,9 +1553,9 @@
mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP);
- pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(__pci_0_00_0, 0xf0, ~(1 << 2));
- pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + pci_or_config8(__pci_0_00_0, 0xf0, 1 << 2); udelay(2);
/* 5 6 7 8 9 10 11 12 */ @@ -1765,9 +1765,9 @@ /* Announce normal operation, initialization completed. */ mchbar_setbits32(DCC_MCHBAR, 0x7 << 16 | 0x1 << 19);
- pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + pci_or_config8(__pci_0_00_0, 0xf0, 1 << 2);
- pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(__pci_0_00_0, 0xf0, ~(1 << 2));
/* Take a breath (the reader). */
@@ -1798,7 +1798,7 @@ dram_optimizations(timings, dimms);
/* Mark raminit being finished. :-) */ - pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); + pci_and_config8(__pci_0_1f_0, 0xa2, (u8)~(1 << 7));
raminit_thermal(sysinfo); init_igd(sysinfo); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 744c92b..9edf83f 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -13,8 +13,8 @@ #include <southbridge/intel/common/pmutil.h> #include <string.h>
-#define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define MCH_DEV PCI_DEV(0, 0, 0) +#define LPC_DEV __pci_0_1f_0 +#define MCH_DEV __pci_0_00_0
void __weak mb_setup_superio(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index f8b418d..5dd483a 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -69,7 +69,7 @@ RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
/* Enable ASPM. */ - if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { + if (LPC_IS_MOBILE(__pci_0_1f_0)) { reg32 = RCBA32(RCBA_DMC); /* Enable mobile specific power saving (set this first). */ reg32 = (reg32 & ~(3 << 10)) | (1 << 10); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index f781098..627830f 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -9,7 +9,7 @@
void i82801ix_lpc_setup(void) { - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *d31f0 = __pci_0_1f_0; const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_i82801ix_config *config;
@@ -45,7 +45,7 @@
void i82801ix_early_init(void) { - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *d31f0 = __pci_0_1f_0;
if (ENV_ROMSTAGE) enable_smbus();
-
Arthur Heymans (Code Review)