Change in coreboot[master]: soc/amd/cezanne/root_complex: generate DPTC ACPI method

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/54074

to look at the new patch set (#2).

Change subject: soc/amd/cezanne/root_complex: generate DPTC ACPI method
......................................................................

soc/amd/cezanne/root_complex: generate DPTC ACPI method

This adds support for convertible devices to support different maximum
power and thermal configurations. The dynamic power and thermal
configuration (DPTC) via ACPI ALIB calls allows to change the parameters
during runtime. This code contains the assumption that
_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At
the moment only chromeec declares EC0.TBMD, but it's also the only code
that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to
the common code directory, since it's currently unsure if we might need
to configure more than those 4 parameters for Cezanne.

Signed-off-by: Felix Held 
Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/root_complex.c
2 files changed, 76 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/54074/2