[M] Change in coreboot[master]: device: Clear lane error status

[Nico Huber (Code Review)]

Attention is currently required from: Wilson Chou, Marc Jones, Jonathan Zhang, Ryback Hung, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Shuming Chu (Shuming).

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 )

Change subject: device: Clear lane error status
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Patch Set 4: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67264/comment/056b7fdd_16a401ec 
PS4, Line 13: at the end of PCIe link training
rather "after all PCIe link training."

Patchset:

PS2:
> No, it’s not suitable to implement that in pciexp_retrain_link() since common clock is hardware desi […]

Well, that's the only link training triggered by corebooot. If we want to do
it for any link training that happened until this point, that's also ok. But
we need to be aware that we'd also clear lane errors that happened after the
link training. Because we have been using the link already at this point.
Maybe that's worth a code comment.