Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54052 )
Change subject: soc/mediatek/mt8195: set dram dma property ......................................................................
soc/mediatek/mt8195: set dram dma property
Set dram dma to be non-cacheable to load blob correctly.
Signed-off-by: Rex-BC Chen rex-bc.chen@mediatek.com Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54052/1
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 67ceed3..a78b7193 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -27,6 +27,10 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += ../common/memory.c ../common/memory_test.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c index 7018093..063402c 100644 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -29,3 +29,11 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} +