Change in ...coreboot[master]: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32283
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate norminal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
BUG=b:129839774 TEST=Calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25mSec of boot performance time.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 161 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/1
diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h new file mode 100644 index 0000000..632e24c --- /dev/null +++ b/src/arch/x86/include/arch/intel-family.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ARCH_INTEL_FAMILY_H +#define ARCH_INTEL_FAMILY_H + +#define INTEL_CORE_YONAH 0x0E + +#define INTEL_CORE2_MEROM 0x0F +#define INTEL_CORE2_MEROM_L 0x16 +#define INTEL_CORE2_PENRYN 0x17 +#define INTEL_CORE2_DUNNINGTON 0x1D + +#define INTEL_NEHALEM 0x1E +/* Auburndale / Havendale */ +#define INTEL_NEHALEM_G 0x1F +#define INTEL_NEHALEM_EP 0x1A +#define INTEL_NEHALEM_EX 0x2E + +#define INTEL_WESTMERE 0x25 +#define INTEL_WESTMERE_EP 0x2C +#define INTEL_WESTMERE_EX 0x2F + +#define INTEL_SANDYBRIDGE 0x2A +#define INTEL_SANDYBRIDGE_X 0x2D +#define INTEL_IVYBRIDGE 0x3A +#define INTEL_IVYBRIDGE_X 0x3E + +#define INTEL_HASWELL_CORE 0x3C +#define INTEL_HASWELL_X 0x3F +#define INTEL_HASWELL_ULT 0x45 +#define INTEL_HASWELL_GT3E 0x46 + +#define INTEL_BROADWELL_CORE 0x3D +#define INTEL_BROADWELL_GT3E 0x47 +#define INTEL_BROADWELL_X 0x4F +#define INTEL_BROADWELL_XEON_D 0x56 + +#define INTEL_SKYLAKE_MOBILE 0x4E +#define INTEL_SKYLAKE_DESKTOP 0x5E +#define INTEL_SKYLAKE_X 0x55 +#define INTEL_KABYLAKE_MOBILE 0x8E +#define INTEL_KABYLAKE_DESKTOP 0x9E +#define INTEL_CANNONLAKE_MOBILE 0x66 +#define INTEL_ICELAKE_MOBILE 0x7E + +/* "Small Core" Processors (Atom) */ + +#define INTEL_ATOM_PINEVIEW 0x1C +#define INTEL_ATOM_LINCROFT 0x26 +#define INTEL_ATOM_PENWELL 0x27 +#define INTEL_ATOM_CLOVERVIEW 0x35 +#define INTEL_ATOM_CEDARVIEW 0x36 +/* BayTrail/BYT / Valleyview */ +#define INTEL_ATOM_SILVERMONT1 0x37 +/* Avaton/Rangely */ +#define INTEL_ATOM_SILVERMONT2 0x4D +/* CherryTrail / Braswell */ +#define INTEL_ATOM_AIRMONT 0x4C +/* Tangier */ +#define INTEL_ATOM_MERRIFIELD 0x4A +/* Anniedale */ +#define INTEL_ATOM_MOOREFIELD 0x5A +#define INTEL_ATOM_GOLDMONT 0x5C +/* Goldmont Microserver */ +#define INTEL_ATOM_DENVERTON 0x5F +#define INTEL_ATOM_GEMINI_LAKE 0x7A + +/* Xeon Phi */ + +/* Knights Landing */ +#define INTEL_XEON_PHI_KNL 0x57 +/* Knights Mill */ +#define INTEL_XEON_PHI_KNM 0x85 + +#endif /* ARCH_INTEL_FAMILY_H */ diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 1298885..a7ff171 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,84 @@ * GNU General Public License for more details. */
+#include <arch/intel-family.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <intelblocks/msr.h>
+static int get_processor_model(void) +{ + union cpuid_01 { + uint32_t eax; + struct { + unsigned stepping_id : 4; + unsigned model : 4; + unsigned family : 4; + unsigned reserved1 : 4; + unsigned ext_model : 4; + unsigned ext_family : 8; + unsigned reserved2 : 4; + } b; + }; + + union cpuid_01 eax_value; + + eax_value.eax = cpuid_eax(1); + + return (eax_value.b.ext_model << 4) | eax_value.b.model; +} + +/* + * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX + * + * Time Stamp Counter + * CPUID Initial EAX value = 0x15 + * EAX Bit 31-0 : An unsigned integer which is the denominator of the + * TSC/"core crystal clock" ratio + * EBX Bit 31-0 : An unsigned interger which is the numerator of the + * TSC/"core crystal clock" ratio + * ECX Bit 31-0 : An unsigned integer which is the nominal frequency of the + * core crystal clock in Hz. + * EDX Bit 31-0 : Reserved = 0 + * + * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 + */ unsigned long tsc_freq_mhz(void) { - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff)); + unsigned int core_crystal_nominal_freq; + struct cpuid_result cpuidr; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuidr = cpuid(0x15); + + if (!cpuidr.ebx || !cpuidr.eax) + return 0; + + core_crystal_nominal_freq = cpuidr.ecx / 1000; + + if (!core_crystal_nominal_freq) { + switch (get_processor_model()) { + case INTEL_SKYLAKE_MOBILE: + case INTEL_SKYLAKE_DESKTOP: + case INTEL_KABYLAKE_MOBILE: + case INTEL_KABYLAKE_DESKTOP: + case INTEL_CANNONLAKE_MOBILE: + case INTEL_ICELAKE_MOBILE: + /* 24.0 MHz */ + core_crystal_nominal_freq = 24000; + break; + case INTEL_ATOM_DENVERTON: + /* 25.0 MHz */ + core_crystal_nominal_freq = 25000; + break; + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GEMINI_LAKE: + /* 19.2 MHz */ + core_crystal_nominal_freq = 19200; + break; + } + } + + return (core_crystal_nominal_freq * cpuidr.ebx / cpuidr.eax) / 1000; }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32283/1/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/1/src/soc/intel/common/block/timer/tim... PS1, Line 51: * EBX Bit 31-0 : An unsigned interger which is the numerator of the 'interger' may be misspelled - perhaps 'integer'?
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#2).
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate norminal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
BUG=b:129839774 TEST=Calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25mSec of boot performance time.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 161 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#3).
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate norminal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
BUG=b:129839774 TEST=Calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25mSec of boot performance time.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 161 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/3
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... PS2, Line 26: struct does this require __packed to make sure the bitfield isn't laid out in 7 words or something crazy like that?
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... PS2, Line 81: core_crystal_nominal_freq if you add _khz to the name, you could drop the comments.
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#4).
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate norminal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
BUG=b:129839774 TEST=Calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25mSec of boot performance time.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 159 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... PS2, Line 26: struct
does this require __packed to make sure the bitfield isn't laid out in 7 words or something crazy li […]
Done
https://review.coreboot.org/#/c/32283/2/src/soc/intel/common/block/timer/tim... PS2, Line 81: core_crystal_nominal_freq
if you add _khz to the name, you could drop the comments.
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4:
(4 comments)
In the header files, you add a lot of new macros also for older generations. Please mention in the commit message, from what generation on method 2 should be used.
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@10 PS3, Line 10: norminal nominal?
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@18 PS3, Line 18: TEST=Calculate TSC frequency using below methods What board is this?
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@25 PS3, Line 25: mSec SI unit is ms.
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@25 PS3, Line 25: Method 2 actually reduce ~25mSec of boot performance time. Awesome. Thank you for documenting that.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4:
Why isn't it implemented in src/cpu/intel/common ?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4:
Why isn't it implemented in src/cpu/intel/common ?
this recommendation is from Gen6 processor onwards platform, hence we didn't move the same into intel/common/.
intel common block what we made is targeted from gen 6 platform onmwards hence should cover all required platform
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@10 PS3, Line 10: norminal
nominal?
Done
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@18 PS3, Line 18: TEST=Calculate TSC frequency using below methods
What board is this?
Done
https://review.coreboot.org/#/c/32283/3//COMMIT_MSG@25 PS3, Line 25: mSec
SI unit is ms.
Done
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#5).
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 159 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/5
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 5: Code-Review-1
(1 comment)
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... PS4, Line 22: static int get_processor_model(void) : { : union cpuid_01 { : uint32_t eax; : struct { : unsigned stepping_id : 4; : unsigned model : 4; : unsigned family : 4; : unsigned reserved1 : 4; : unsigned ext_model : 4; : unsigned ext_family : 8; : unsigned reserved2 : 4; : } __packed fields; : }; : : union cpuid_01 eax_value; : : eax_value.eax = cpuid_eax(1); : : return (eax_value.fields.ext_model << 4) | eax_value.fields.model; : } Please don't reinvent the wheel, use get_fms().
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... PS4, Line 22: static int get_processor_model(void) : { : union cpuid_01 { : uint32_t eax; : struct { : unsigned stepping_id : 4; : unsigned model : 4; : unsigned family : 4; : unsigned reserved1 : 4; : unsigned ext_model : 4; : unsigned ext_family : 8; : unsigned reserved2 : 4; : } __packed fields; : }; : : union cpuid_01 eax_value; : : eax_value.eax = cpuid_eax(1); : : return (eax_value.fields.ext_model << 4) | eax_value.fields.model; : }
Please don't reinvent the wheel, use get_fms().
let me check that get_fms(&c, cpuid_eax(1)) is something what can be done i guess.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32283/5/src/arch/x86/include/arch/intel-fami... File src/arch/x86/include/arch/intel-family.h:
https://review.coreboot.org/#/c/32283/5/src/arch/x86/include/arch/intel-fami... PS5, Line 17: It might be good to prefix these all with CPUID_ or CPU_MODEL_ or something to distinguish where these values come from.
But, if you didn't run into any name conflicts maybe it is fine...
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#6).
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 147 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/32283/5/src/arch/x86/include/arch/intel-fami... File src/arch/x86/include/arch/intel-family.h:
https://review.coreboot.org/#/c/32283/5/src/arch/x86/include/arch/intel-fami... PS5, Line 17:
It might be good to prefix these all with CPUID_ or CPU_MODEL_ or something to distinguish where the […]
Done
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/#/c/32283/4/src/soc/intel/common/block/timer/tim... PS4, Line 22: static int get_processor_model(void) : { : union cpuid_01 { : uint32_t eax; : struct { : unsigned stepping_id : 4; : unsigned model : 4; : unsigned family : 4; : unsigned reserved1 : 4; : unsigned ext_model : 4; : unsigned ext_family : 8; : unsigned reserved2 : 4; : } __packed fields; : }; : : union cpuid_01 eax_value; : : eax_value.eax = cpuid_eax(1); : : return (eax_value.fields.ext_model << 4) | eax_value.fields.model; : }
let me check that […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 6:
any further review?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 6: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
Patch Set 6:
any further review?
@Patrick G: can you please review.
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32283 )
Change subject: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-by: Aamir Bohra aamir.bohra@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 147 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve
diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h new file mode 100644 index 0000000..43eb0e6 --- /dev/null +++ b/src/arch/x86/include/arch/intel-family.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ARCH_INTEL_FAMILY_H +#define ARCH_INTEL_FAMILY_H + +#define CPU_MODEL_INTEL_CORE_YONAH 0x0E + +#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F +#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16 +#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17 +#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D + +#define CPU_MODEL_INTEL_NEHALEM 0x1E +/* Auburndale / Havendale */ +#define CPU_MODEL_INTEL_NEHALEM_G 0x1F +#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A +#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E + +#define CPU_MODEL_INTEL_WESTMERE 0x25 +#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C +#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F + +#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A +#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D +#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A +#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E + +#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C +#define CPU_MODEL_INTEL_HASWELL_X 0x3F +#define CPU_MODEL_INTEL_HASWELL_ULT 0x45 +#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46 + +#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D +#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47 +#define CPU_MODEL_INTEL_BROADWELL_X 0x4F +#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56 + +#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E +#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E +#define CPU_MODEL_INTEL_SKYLAKE_X 0x55 +#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E +#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E +#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66 +#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E + +/* "Small Core" Processors (Atom) */ + +#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C +#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26 +#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27 +#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35 +#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36 +/* BayTrail/BYT / Valleyview */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37 +/* Avaton/Rangely */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D +/* CherryTrail / Braswell */ +#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C +/* Tangier */ +#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A +/* Anniedale */ +#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A +#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C +/* Goldmont Microserver */ +#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F +#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A + +/* Xeon Phi */ + +/* Knights Landing */ +#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57 +/* Knights Mill */ +#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85 + +#endif /* ARCH_INTEL_FAMILY_H */ diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 1298885..e60ac4d 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,70 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> +#include <arch/intel-family.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <intelblocks/msr.h>
+static int get_processor_model(void) +{ + struct cpuinfo_x86 c; + + get_fms(&c, cpuid_eax(1)); + + return c.x86_model; +} + +/* + * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX + * + * Time Stamp Counter + * CPUID Initial EAX value = 0x15 + * EAX Bit 31-0 : An unsigned integer which is the denominator of the + * TSC/"core crystal clock" ratio + * EBX Bit 31-0 : An unsigned integer which is the numerator of the + * TSC/"core crystal clock" ratio + * ECX Bit 31-0 : An unsigned integer which is the nominal frequency of the + * core crystal clock in Hz. + * EDX Bit 31-0 : Reserved = 0 + * + * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 + */ unsigned long tsc_freq_mhz(void) { - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff)); + unsigned int core_crystal_nominal_freq_khz; + struct cpuid_result cpuidr; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuidr = cpuid(0x15); + + if (!cpuidr.ebx || !cpuidr.eax) + return 0; + + core_crystal_nominal_freq_khz = cpuidr.ecx / 1000; + + if (!core_crystal_nominal_freq_khz) { + switch (get_processor_model()) { + case CPU_MODEL_INTEL_SKYLAKE_MOBILE: + case CPU_MODEL_INTEL_SKYLAKE_DESKTOP: + case CPU_MODEL_INTEL_KABYLAKE_MOBILE: + case CPU_MODEL_INTEL_KABYLAKE_DESKTOP: + case CPU_MODEL_INTEL_CANNONLAKE_MOBILE: + case CPU_MODEL_INTEL_ICELAKE_MOBILE: + core_crystal_nominal_freq_khz = 24000; + break; + case CPU_MODEL_INTEL_ATOM_DENVERTON: + core_crystal_nominal_freq_khz = 25000; + break; + case CPU_MODEL_INTEL_ATOM_GOLDMONT: + case CPU_MODEL_INTEL_ATOM_GEMINI_LAKE: + core_crystal_nominal_freq_khz = 19200; + break; + } + } + + return (core_crystal_nominal_freq_khz * cpuidr.ebx / cpuidr.eax) / + 1000; }
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Subrata Banik (Code Review)