Attention is currently required from: Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik.
Avi Uday has posted comments on this change by Avi Uday. ( https://review.coreboot.org/c/coreboot/+/87351?usp=email )
Change subject: mb/google/ocelot: Update Ocelot board ......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/87351/comment/50dfd5e8_04c375cc?usp... : PS2, Line 65: # As per document 813278, the Intel PTL-U 15W SoC supports : # Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System : # Agent (SA). The ICC Limit is represented in 1/4 A : # increments, i.e., a value of 400 = 100A. : # IA VR configuration : register "enable_fast_vmode[VR_DOMAIN_IA]" = "true" : register "cep_enable[VR_DOMAIN_IA]" = "true" : register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A : # GT VR configuration : register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" : register "cep_enable[VR_DOMAIN_GT]" = "true" : register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A : # SA VR configuration : register "enable_fast_vmode[VR_DOMAIN_SA]" = "true" : register "cep_enable[VR_DOMAIN_SA]" = "true" : register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A
this is SoC specific and better we don't copy from fatcat
Done
File src/mainboard/google/ocelot/variants/ocelot/fw_config.c:
https://review.coreboot.org/c/coreboot/+/87351/comment/36a945ec_5a4eedf6?usp... : PS2, Line 164: PAD_NC(GPP_D16, NONE),
please rebase on top of https://review.coreboot. […]
Done
File src/mainboard/google/ocelot/variants/ocelot/gpio.c:
https://review.coreboot.org/c/coreboot/+/87351/comment/d1d39d61_80679fbe?usp... : PS2, Line 225: /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */
Till then should I keep this? […]
Done
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Avi Uday (Code Review)