Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger Lake - coreboot-gerrit

22 Jan 2020

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38524 )
Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger Lake
......................................................................
vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger Lake
Update FSP header files for Tiger Lake platform version 2457.
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Change-Id: I8038d5d7890ff9d231b36477553621829b31d5e6
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
2 files changed, 122 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38524/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
old mode 100644
new mode 100755
index f37e56c..641f3fc
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -1,6 +1,6 @@
 /** @file
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -367,7 +367,37 @@
/** Offset 0x026E - Reserved
 **/
-  UINT8                       Reserved12[8];
+  UINT8                       Reserved12[3];
+
+/** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device
+  0=Disabled,1(Default)=eDP, 2=MIPI DSI
+  0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+  UINT8                       DdiPortAConfig;
+
+/** Offset 0x0272 - Program GPIOs for LFP on DDI port-B device
+  0(Default)=Disabled,1=eDP, 2=MIPI DSI
+  0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+  UINT8                       DdiPortBConfig;
+
+/** Offset 0x0273 - Enable or disable HPD of DDI port A
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortAHpd;
+
+/** Offset 0x0274 - Enable or disable HPD of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBHpd;
+
+/** Offset 0x0275 - Enable or disable HPD of DDI port C
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCHpd;
/** Offset 0x0276 - Enable or disable HPD of DDI port 1
   0=Disable, 1(Default)=Enable
@@ -375,9 +405,41 @@
 **/
   UINT8                       DdiPort1Hpd;
-/** Offset 0x0277 - Reserved
+/** Offset 0x0277 - Enable or disable HPD of DDI port 2
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved13[6];
+  UINT8                       DdiPort2Hpd;
+
+/** Offset 0x0278 - Enable or disable HPD of DDI port 3
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort3Hpd;
+
+/** Offset 0x0279 - Enable or disable HPD of DDI port 4
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort4Hpd;
+
+/** Offset 0x027A - Enable or disable DDC of DDI port A
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortADdc;
+
+/** Offset 0x027B - Enable or disable DDC of DDI port B
+  0=Disable, 1(Default)=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortBDdc;
+
+/** Offset 0x027C - Enable or disable DDC of DDI port C
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPortCDdc;
/** Offset 0x027D - Enable DDC setting of DDI Port 1
   0(Default)=Disable, 1=Enable
@@ -385,9 +447,27 @@
 **/
   UINT8                       DdiPort1Ddc;
-/** Offset 0x027E - Reserved
+/** Offset 0x027E - Enable DDC setting of DDI Port 2
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
 **/
-  UINT8                       Reserved14[129];
+  UINT8                       DdiPort2Ddc;
+
+/** Offset 0x027F - Enable DDC setting of DDI Port 3
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort3Ddc;
+
+/** Offset 0x0280 - Enable DDC setting of DDI Port 4
+  0(Default)=Disable, 1=Enable
+  $EN_DIS
+**/
+  UINT8                       DdiPort4Ddc;
+
+/** Offset 0x0281 - Reserved
+**/
+  UINT8                       Reserved13[126];
/** Offset 0x02FF - DMI Gen3 Root port preset values per lane
   Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@@ -396,7 +476,7 @@
/** Offset 0x0307 - Reserved
 **/
-  UINT8                       Reserved15[22];
+  UINT8                       Reserved14[22];
/** Offset 0x031D - C6DRAM power gating feature
   This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
@@ -408,7 +488,7 @@
/** Offset 0x031E - Reserved
 **/
-  UINT8                       Reserved16[5];
+  UINT8                       Reserved15[5];
/** Offset 0x0323 - Hyper Threading Enable/Disable
   Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
@@ -418,7 +498,7 @@
/** Offset 0x0324 - Reserved
 **/
-  UINT8                       Reserved17;
+  UINT8                       Reserved16;
/** Offset 0x0325 - CPU ratio value
   CPU ratio value. Valid Range 0 to 63
@@ -427,7 +507,7 @@
/** Offset 0x0326 - Reserved
 **/
-  UINT8                       Reserved18[2];
+  UINT8                       Reserved17[2];
/** Offset 0x0328 - Processor Early Power On Configuration FCLK setting
   <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
@@ -438,7 +518,7 @@
/** Offset 0x0329 - Reserved
 **/
-  UINT8                       Reserved19;
+  UINT8                       Reserved18;
/** Offset 0x032A - Enable or Disable VMX
   Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
@@ -448,7 +528,7 @@
/** Offset 0x032B - Reserved
 **/
-  UINT8                       Reserved20[31];
+  UINT8                       Reserved19[31];
/** Offset 0x034A - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -462,7 +542,7 @@
/** Offset 0x034C - Reserved
 **/
-  UINT8                       Reserved21[4];
+  UINT8                       Reserved20[4];
/** Offset 0x0350 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -476,7 +556,7 @@
/** Offset 0x0358 - Reserved
 **/
-  UINT8                      Reserved22[8];
+  UINT8                      Reserved21[8];
/** Offset 0x0360 - TxtHeapMemorySize
   Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
@@ -490,7 +570,7 @@
/** Offset 0x0368 - Reserved
 **/
-  UINT8                      Reserved23[522];
+  UINT8                      Reserved22[522];
/** Offset 0x0572 - Number of RsvdSmbusAddressTable.
   The number of elements in the RsvdSmbusAddressTable.
@@ -499,7 +579,7 @@
/** Offset 0x0573 - Reserved
 **/
-  UINT8                       Reserved24[4];
+  UINT8                       Reserved23[4];
/** Offset 0x0577 - Usage type for ClkSrc
   0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
@@ -507,9 +587,14 @@
 **/
   UINT8                       PcieClkSrcUsage[16];
-/** Offset 0x0587 - Reserved
+/** Offset 0x0587 - ClkReq-to-ClkSrc mapping
+  Number of ClkReq signal assigned to ClkSrc
 **/
-  UINT8                       Reserved25[21];
+  UINT8                       PcieClkSrcClkReq[16];
+
+/** Offset 0x0597 - Reserved
+**/
+  UINT8                       Reserved24[5];
/** Offset 0x059C - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -532,7 +617,7 @@
/** Offset 0x05A2 - Reserved
 **/
-  UINT8                       Reserved26[14];
+  UINT8                       Reserved25[14];
/** Offset 0x05B0 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -542,7 +627,7 @@
/** Offset 0x05B1 - Reserved
 **/
-  UINT8                       Reserved27[4];
+  UINT8                       Reserved26[4];
/** Offset 0x05B5 - MRC Safe Config
   Enables/Disable MRC Safe Config
@@ -588,7 +673,7 @@
/** Offset 0x05BC - Reserved
 **/
-  UINT8                       Reserved28[4];
+  UINT8                       Reserved27[4];
/** Offset 0x05C0 - Early Command Training
   Enables/Disable Early Command Training
@@ -598,7 +683,7 @@
/** Offset 0x05C1 - Reserved
 **/
-  UINT8                       Reserved29[109];
+  UINT8                       Reserved28[109];
/** Offset 0x062E - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -608,7 +693,7 @@
/** Offset 0x0630 - Reserved
 **/
-  UINT8                      Reserved30[62];
+  UINT8                      Reserved29[62];
/** Offset 0x066E - PcdSerialDebugLevel
   Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
@@ -621,7 +706,7 @@
/** Offset 0x066F - Reserved
 **/
-  UINT8                       Reserved31[2];
+  UINT8                       Reserved30[2];
/** Offset 0x0671 - Safe Mode Support
   This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
@@ -631,7 +716,7 @@
/** Offset 0x0672 - Reserved
 **/
-  UINT8                       Reserved32[2];
+  UINT8                       Reserved31[2];
/** Offset 0x0674 - TCSS USB Port Enable
   Bitmap for per port enabling
@@ -640,7 +725,7 @@
/** Offset 0x0675 - Reserved
 **/
-  UINT8                       Reserved33[80];
+  UINT8                       Reserved32[80];
/** Offset 0x06C5 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -651,7 +736,7 @@
/** Offset 0x06C6 - Reserved
 **/
-  UINT8                       Reserved34[2];
+  UINT8                       Reserved33[2];
/** Offset 0x06C8 - Lock PCU Thermal Management registers
   Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
@@ -661,7 +746,7 @@
/** Offset 0x06C9 - Reserved
 **/
-  UINT8                       Reserved35[122];
+  UINT8                       Reserved34[122];
/** Offset 0x0743 - Enable HD Audio Link
   Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
@@ -671,7 +756,7 @@
/** Offset 0x0744 - Reserved
 **/
-  UINT8                       Reserved36[3];
+  UINT8                       Reserved35[3];
/** Offset 0x0747 - Enable HD Audio DMIC_N Link
   Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
@@ -680,7 +765,7 @@
/** Offset 0x0749 - Reserved
 **/
-  UINT8                       Reserved37[3];
+  UINT8                       Reserved36[3];
/** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -700,7 +785,7 @@
/** Offset 0x075D - Reserved
 **/
-  UINT8                       Reserved38[3];
+  UINT8                       Reserved37[3];
/** Offset 0x0760 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -737,7 +822,7 @@
/** Offset 0x0775 - Reserved
 **/
-  UINT8                       Reserved39[315];
+  UINT8                       Reserved38[355];
 } FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -756,11 +841,11 @@
 **/
   FSP_M_CONFIG                FspmConfig;
-/** Offset 0x08B0
+/** Offset 0x08D8
 **/
-  UINT8                       UnusedUpdSpace23[6];
+  UINT8                       UnusedUpdSpace24[6];
-/** Offset 0x08B6
+/** Offset 0x08DE
 **/
   UINT16                      UpdTerminator;
 } FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
old mode 100644
new mode 100755
index 69f27b9..6cf3668
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
@@ -1,6 +1,6 @@
 /** @file
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -385,7 +385,7 @@
/** Offset 0x03FE - HECI3 state
   The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
-  0: disable, 1: enable
+  DEPRECATED 0: disable, 1: enable
   $EN_DIS
 **/
   UINT8                       Heci3Enabled;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8038d5d7890ff9d231b36477553621829b31d5e6
Gerrit-Change-Number: 38524
Gerrit-PatchSet: 1
Gerrit-Owner: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Gerrit-MessageType: newchange



    