Change in coreboot[master]: mb/intel/adlrvp_m: Enable LTR for PCIE

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54492 )

Change subject: mb/intel/adlrvp_m: Enable LTR for PCIE
......................................................................

mb/intel/adlrvp_m: Enable LTR for PCIE

BUG=none
TEST=Use command $ lspci -vv
     LTR+ is listed on DevCtl2

Signed-off-by: Bernardo Perez Priego 
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/devicetree_m.cb
1 file changed, 8 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Ryan A Albazzaz: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 9c66bd7..4e4135f 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -42,28 +42,32 @@
    register "pch_pcie_rp[PCH_RP(4)]" = "{
    	.clk_src = 5,
    	.clk_req = 5,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
    }"

# Enable PCH PCIE RP 5 using CLK 2
    register "pch_pcie_rp[PCH_RP(5)]" = "{
    	.clk_src = 2,
    	.clk_req = 2,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
    }"

# Enable PCH PCIE RP 9 using CLK 3
    register "pch_pcie_rp[PCH_RP(9)]" = "{
    	.clk_src = 3,
    	.clk_req = 3,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
    }"

#Enable PCH PCIE RP 10 using CLK 1
    register "pch_pcie_rp[PCH_RP(10)]" = "{
    	.clk_src = 1,
    	.clk_req = 1,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
+		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+		.PcieRpL1Substates = L1_SS_L1_2,
    }"

# Hybrid storage mode