Change in coreboot[master]: soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig

[Nico Huber (Code Review)]

Attention is currently required from:  Felix Singer, Michael Niewöhner.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 )

Change subject: soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig
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Patch Set 43:

(1 comment)

Patchset:

PS42: 
Sorry, obviously I was commenting too hastily last night and mixed some
things up.
> Disabling the (hardware) timer on platforms without emulation support will violate ACPI - or is that what you mean they changed?

Yes, that's what I found out after my first comment. In ACPI <= 4 the
PM timer was mandatory. Since ACPI 5 it's optional. I guess compliance
(with neither hardware nor emulation enabled) would depend on what FADT
version we advertise.
> > How do we know that these chips don't have it?
>
> APL doesn't have the hardware timer but only emulation. You were the one finding that out, some time ago, looking at the APL datasheets ;-) Also you looked at BWG for various platforms. You also mentioned "BIOS Specification for Skylake..Comet Lake".
>
> Denverton and Xeon_SP either don't have the emulation or we just couldn't find out... I don't remember anymore. Anyway, that's why the Kconfig PM_ACPI_TIMER_OPTIONAL was created.

I can't say that I'd still remember things, but that Kconfig effectively
guards the user visible one. So I'd say it does not reflect what the hardware
can do but what the current state of the coreboot port can do.