Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Do cosmetic fixes ......................................................................
soc/intel/skylake: Do cosmetic fixes
This is mostly line reflowing to make use of the increased line length limit of 96 characters.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/fspcar.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c 39 files changed, 561 insertions(+), 1,015 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index ccfc7b7..649220f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -191,8 +191,7 @@ /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif @@ -225,8 +224,7 @@ current = acpi_create_madt_lapics(current);
/* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current); } @@ -526,15 +524,13 @@
/* Generate processor _PR.CPUx */ acpigen_write_processor( - cpu_id*cores_per_package+core_id, - pcontrol_blk, plen); + cpu_id*cores_per_package+core_id, pcontrol_blk, plen); /* Generate C-state tables */ generate_c_state_entries(is_s0ix_enable);
if (config->eist_enable) { /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + generate_p_state_entries(core_id, cores_per_package); if (config->speed_shift_enable) acpigen_write_CPPC_method(); } @@ -569,8 +565,8 @@ /* Add RMRR entry */ tmp = current;
- current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(), + sa_get_tolud_base() - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } @@ -606,8 +602,7 @@ return current; }
-unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { const struct soc_intel_skylake_config *const config = config_of(dev); @@ -648,12 +643,10 @@ return current; }
-unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - current = acpi_write_dbg2_pci_uart(rsdp, current, - uart_get_device(), + current = acpi_write_dbg2_pci_uart(rsdp, current, uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); current = acpi_write_hpet(device, current, rsdp); return acpi_align_current(current); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index e9ca2d8..2b788c6 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..1ec9f5d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -93,19 +93,16 @@ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
/* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the PWRMBASE to be 64KB aligned. * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be - * 64KB in size. + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the memory allocated to PWRMBASE to be 64KB in size. */ pcr_write32(PID_DMI, PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else @@ -116,10 +113,7 @@ { uint32_t dmi_control;
- /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ + /* This cycle decoding is only allowed to set when DMICTL.SRLOCK is 0. */ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); if (dmi_control & PCR_DMI_DMICTL_SRLOCK) return -1; @@ -128,8 +122,7 @@
void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
/* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) @@ -152,19 +145,13 @@
void pch_early_init(void) { - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ + /* Enable ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, GPE0_STS, GPE0_EN registers. */ soc_config_acpibase();
- /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ + /* Enable PWRM Base for accessing Global Reset Cause Register. */ soc_config_pwrmbase();
- /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure();
/* Program SMBUS_BASE_ADDRESS and Enable it */ diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e65d9a..c7c1c5e 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -94,12 +94,9 @@ { PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, - "Kabylake-Y iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, - "Kabylake-U iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, - "Kabylake-U iHDCP 2.2 Base" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, "Kabylake-U iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, "Kabylake-U iHDCP 2.2 Base" }, };
static struct { @@ -181,8 +178,7 @@ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); }
@@ -269,8 +265,7 @@
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); printk(BIOS_DEBUG, " rank interleave %s\n", diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..3a6decd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -100,18 +100,12 @@ sizeof(params->SerialIoDevMode));
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; }
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -119,8 +113,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -129,14 +122,12 @@ } }
- memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); + memcpy(params->PcieRpEnable, config->PcieRpEnable, sizeof(params->PcieRpEnable)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug));
params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; @@ -178,10 +169,8 @@ if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
- params->WakeConfigWolEnableOverride = - config->WakeConfigWolEnableOverride; - params->WakeConfigPcieWakeFromDeepSx = - config->WakeConfigPcieWakeFromDeepSx; + params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride; + params->WakeConfigPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PmConfigDeepSxPol = config->PmConfigDeepSxPol; params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert; params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert; @@ -189,14 +178,11 @@ params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PmConfigPciClockRun = config->PmConfigPciClockRun; params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PmConfigPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; - params->SerialIrqConfigSirqMode = - config->serirq_mode == SERIRQ_CONTINUOUS; - params->SerialIrqConfigStartFramePulse = - config->SerialIrqConfigStartFramePulse; + params->SerialIrqConfigSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; + params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
@@ -204,11 +190,9 @@ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/* - * To disable Heci, the Psf needs to be left unlocked - * by FSP after end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in coreboot - * + * To disable Heci, the Psf needs to be left unlocked by FSP after end of post + * sequence. Based on the devicetree setting, we set the appropriate PsfUnlock + * policy in Fsp, do the changes and then lock it back in coreboot. */ if (config->HeciEnabled == 0) params->PsfUnlock = 1; @@ -249,8 +233,8 @@ /* Display the parameters for SiliconInit */ printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); fsp_display_upd_value("LogoPtr", 4, - (uint32_t)original->LogoPtr, - (uint32_t)params->LogoPtr); + (uint32_t)original->LogoPtr, + (uint32_t)params->LogoPtr); fsp_display_upd_value("LogoSize", 4, (uint32_t)original->LogoSize, (uint32_t)params->LogoSize); @@ -266,8 +250,7 @@ fsp_display_upd_value("TurboMode", 1, (uint32_t)original->TurboMode, (uint32_t)params->TurboMode); - fsp_display_upd_value("Device4Enable", 1, - original->Device4Enable, + fsp_display_upd_value("Device4Enable", 1, original->Device4Enable, params->Device4Enable); fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0], params->PcieRpEnable[0]); @@ -309,130 +292,89 @@ params->PcieRpEnable[18]); fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19], params->PcieRpEnable[19]); - fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, - original->PcieRpClkReqSupport[0], + fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, original->PcieRpClkReqSupport[0], params->PcieRpClkReqSupport[0]); - fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, - original->PcieRpClkReqSupport[1], + fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, original->PcieRpClkReqSupport[1], params->PcieRpClkReqSupport[1]); - fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, - original->PcieRpClkReqSupport[2], + fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, original->PcieRpClkReqSupport[2], params->PcieRpClkReqSupport[2]); - fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, - original->PcieRpClkReqSupport[3], + fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, original->PcieRpClkReqSupport[3], params->PcieRpClkReqSupport[3]); - fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, - original->PcieRpClkReqSupport[4], + fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, original->PcieRpClkReqSupport[4], params->PcieRpClkReqSupport[4]); - fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, - original->PcieRpClkReqSupport[5], + fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, original->PcieRpClkReqSupport[5], params->PcieRpClkReqSupport[5]); - fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, - original->PcieRpClkReqSupport[6], + fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, original->PcieRpClkReqSupport[6], params->PcieRpClkReqSupport[6]); - fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, - original->PcieRpClkReqSupport[7], + fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, original->PcieRpClkReqSupport[7], params->PcieRpClkReqSupport[7]); - fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, - original->PcieRpClkReqSupport[8], + fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, original->PcieRpClkReqSupport[8], params->PcieRpClkReqSupport[8]); - fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, - original->PcieRpClkReqSupport[9], + fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, original->PcieRpClkReqSupport[9], params->PcieRpClkReqSupport[9]); - fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, - original->PcieRpClkReqSupport[10], + fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, original->PcieRpClkReqSupport[10], params->PcieRpClkReqSupport[10]); - fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, - original->PcieRpClkReqSupport[11], + fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, original->PcieRpClkReqSupport[11], params->PcieRpClkReqSupport[11]); - fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, - original->PcieRpClkReqSupport[12], + fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, original->PcieRpClkReqSupport[12], params->PcieRpClkReqSupport[12]); - fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, - original->PcieRpClkReqSupport[13], + fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, original->PcieRpClkReqSupport[13], params->PcieRpClkReqSupport[13]); - fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, - original->PcieRpClkReqSupport[14], + fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, original->PcieRpClkReqSupport[14], params->PcieRpClkReqSupport[14]); - fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, - original->PcieRpClkReqSupport[15], + fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, original->PcieRpClkReqSupport[15], params->PcieRpClkReqSupport[15]); - fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, - original->PcieRpClkReqSupport[16], + fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, original->PcieRpClkReqSupport[16], params->PcieRpClkReqSupport[16]); - fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, - original->PcieRpClkReqSupport[17], + fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, original->PcieRpClkReqSupport[17], params->PcieRpClkReqSupport[17]); - fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, - original->PcieRpClkReqSupport[18], + fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, original->PcieRpClkReqSupport[18], params->PcieRpClkReqSupport[18]); - fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, - original->PcieRpClkReqSupport[19], + fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, original->PcieRpClkReqSupport[19], params->PcieRpClkReqSupport[19]); - fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, - original->PcieRpClkReqNumber[0], + fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, original->PcieRpClkReqNumber[0], params->PcieRpClkReqNumber[0]); - fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, - original->PcieRpClkReqNumber[1], + fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, original->PcieRpClkReqNumber[1], params->PcieRpClkReqNumber[1]); - fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, - original->PcieRpClkReqNumber[2], + fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, original->PcieRpClkReqNumber[2], params->PcieRpClkReqNumber[2]); - fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, - original->PcieRpClkReqNumber[3], + fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, original->PcieRpClkReqNumber[3], params->PcieRpClkReqNumber[3]); - fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, - original->PcieRpClkReqNumber[4], + fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, original->PcieRpClkReqNumber[4], params->PcieRpClkReqNumber[4]); - fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, - original->PcieRpClkReqNumber[5], + fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, original->PcieRpClkReqNumber[5], params->PcieRpClkReqNumber[5]); - fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, - original->PcieRpClkReqNumber[6], + fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, original->PcieRpClkReqNumber[6], params->PcieRpClkReqNumber[6]); - fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, - original->PcieRpClkReqNumber[7], + fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, original->PcieRpClkReqNumber[7], params->PcieRpClkReqNumber[7]); - fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, - original->PcieRpClkReqNumber[8], + fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, original->PcieRpClkReqNumber[8], params->PcieRpClkReqNumber[8]); - fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, - original->PcieRpClkReqNumber[9], + fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, original->PcieRpClkReqNumber[9], params->PcieRpClkReqNumber[9]); - fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, - original->PcieRpClkReqNumber[10], + fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, original->PcieRpClkReqNumber[10], params->PcieRpClkReqNumber[10]); - fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, - original->PcieRpClkReqNumber[11], + fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, original->PcieRpClkReqNumber[11], params->PcieRpClkReqNumber[11]); - fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, - original->PcieRpClkReqNumber[12], + fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, original->PcieRpClkReqNumber[12], params->PcieRpClkReqNumber[12]); - fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, - original->PcieRpClkReqNumber[13], + fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, original->PcieRpClkReqNumber[13], params->PcieRpClkReqNumber[13]); - fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, - original->PcieRpClkReqNumber[14], + fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, original->PcieRpClkReqNumber[14], params->PcieRpClkReqNumber[14]); - fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, - original->PcieRpClkReqNumber[15], + fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, original->PcieRpClkReqNumber[15], params->PcieRpClkReqNumber[15]); - fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, - original->PcieRpClkReqNumber[16], + fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, original->PcieRpClkReqNumber[16], params->PcieRpClkReqNumber[16]); - fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, - original->PcieRpClkReqNumber[17], + fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, original->PcieRpClkReqNumber[17], params->PcieRpClkReqNumber[17]); - fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, - original->PcieRpClkReqNumber[18], + fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, original->PcieRpClkReqNumber[18], params->PcieRpClkReqNumber[18]); - fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, - original->PcieRpClkReqNumber[19], + fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, original->PcieRpClkReqNumber[19], params->PcieRpClkReqNumber[19]); - fsp_display_upd_value("EnableLan", 1, original->EnableLan, - params->EnableLan); - fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, - params->Cio2Enable); + + fsp_display_upd_value("EnableLan", 1, original->EnableLan, params->EnableLan); + fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, params->Cio2Enable); fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, params->SataSalpSupport); fsp_display_upd_value("SataPortsEnable[0]", 1, @@ -467,10 +409,8 @@ original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); fsp_display_upd_value("SataPortsDevSlp[7]", 1, original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); - fsp_display_upd_value("EnableAzalia", 1, - original->EnableAzalia, params->EnableAzalia); - fsp_display_upd_value("DspEnable", 1, original->DspEnable, - params->DspEnable); + fsp_display_upd_value("EnableAzalia", 1, original->EnableAzalia, params->EnableAzalia); + fsp_display_upd_value("DspEnable", 1, original->DspEnable, params->DspEnable); fsp_display_upd_value("IoBufferOwnership", 1, original->IoBufferOwnership, params->IoBufferOwnership); fsp_display_upd_value("PortUsb20Enable[0]", 1, @@ -525,12 +465,10 @@ original->PortUsb30Enable[8], params->PortUsb30Enable[8]); fsp_display_upd_value("PortUsb30Enable[9]", 1, original->PortUsb30Enable[9], params->PortUsb30Enable[9]); - fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, - params->XdciEnable); - fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, - params->SsicPortEnable); - fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, - params->SmbusEnable); + fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, params->XdciEnable); + fsp_display_upd_value("SsicPortEnable", 1, + original->SsicPortEnable, params->SsicPortEnable); + fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, params->SmbusEnable); fsp_display_upd_value("SerialIoDevMode[0]", 1, original->SerialIoDevMode[0], params->SerialIoDevMode[0]); fsp_display_upd_value("SerialIoDevMode[1]", 1, @@ -559,10 +497,9 @@ original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, params->ScsSdCardEnabled); - fsp_display_upd_value("IshEnable", 1, original->IshEnable, - params->IshEnable); - fsp_display_upd_value("ShowSpiController", 1, - original->ShowSpiController, params->ShowSpiController); + fsp_display_upd_value("IshEnable", 1, original->IshEnable, params->IshEnable); + fsp_display_upd_value("ShowSpiController", 1, original->ShowSpiController, + params->ShowSpiController); fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging, params->HsioMessaging); fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, @@ -571,45 +508,28 @@ params->EnableSata); fsp_display_upd_value("SataMode", 1, original->SataMode, params->SataMode); - fsp_display_upd_value("NumOfDevIntConfig", 1, - original->NumOfDevIntConfig, + fsp_display_upd_value("NumOfDevIntConfig", 1, original->NumOfDevIntConfig, params->NumOfDevIntConfig); - fsp_display_upd_value("PxRcConfig[PARC]", 1, - original->PxRcConfig[PCH_PARC], + fsp_display_upd_value("PxRcConfig[PARC]", 1, original->PxRcConfig[PCH_PARC], params->PxRcConfig[PCH_PARC]); - fsp_display_upd_value("PxRcConfig[PBRC]", 1, - original->PxRcConfig[PCH_PBRC], + fsp_display_upd_value("PxRcConfig[PBRC]", 1, original->PxRcConfig[PCH_PBRC], params->PxRcConfig[PCH_PBRC]); - fsp_display_upd_value("PxRcConfig[PCRC]", 1, - original->PxRcConfig[PCH_PCRC], + fsp_display_upd_value("PxRcConfig[PCRC]", 1, original->PxRcConfig[PCH_PCRC], params->PxRcConfig[PCH_PCRC]); - fsp_display_upd_value("PxRcConfig[PDRC]", 1, - original->PxRcConfig[PCH_PDRC], + fsp_display_upd_value("PxRcConfig[PDRC]", 1, original->PxRcConfig[PCH_PDRC], params->PxRcConfig[PCH_PDRC]); - fsp_display_upd_value("PxRcConfig[PERC]", 1, - original->PxRcConfig[PCH_PERC], + fsp_display_upd_value("PxRcConfig[PERC]", 1, original->PxRcConfig[PCH_PERC], params->PxRcConfig[PCH_PERC]); - fsp_display_upd_value("PxRcConfig[PFRC]", 1, - original->PxRcConfig[PCH_PFRC], + fsp_display_upd_value("PxRcConfig[PFRC]", 1, original->PxRcConfig[PCH_PFRC], params->PxRcConfig[PCH_PFRC]); - fsp_display_upd_value("PxRcConfig[PGRC]", 1, - original->PxRcConfig[PCH_PGRC], + fsp_display_upd_value("PxRcConfig[PGRC]", 1, original->PxRcConfig[PCH_PGRC], params->PxRcConfig[PCH_PGRC]); - fsp_display_upd_value("PxRcConfig[PHRC]", 1, - original->PxRcConfig[PCH_PHRC], + fsp_display_upd_value("PxRcConfig[PHRC]", 1, original->PxRcConfig[PCH_PHRC], params->PxRcConfig[PCH_PHRC]); - fsp_display_upd_value("GpioIrqRoute", 1, - original->GpioIrqRoute, - params->GpioIrqRoute); - fsp_display_upd_value("SciIrqSelect", 1, - original->SciIrqSelect, - params->SciIrqSelect); - fsp_display_upd_value("TcoIrqSelect", 1, - original->TcoIrqSelect, - params->TcoIrqSelect); - fsp_display_upd_value("TcoIrqEnable", 1, - original->TcoIrqEnable, - params->TcoIrqEnable); + fsp_display_upd_value("GpioIrqRoute", 1, original->GpioIrqRoute, params->GpioIrqRoute); + fsp_display_upd_value("SciIrqSelect", 1, original->SciIrqSelect, params->SciIrqSelect); + fsp_display_upd_value("TcoIrqSelect", 1, original->TcoIrqSelect, params->TcoIrqSelect); + fsp_display_upd_value("TcoIrqEnable", 1, original->TcoIrqEnable, params->TcoIrqEnable); fsp_display_upd_value("LockDownConfigGlobalSmi", 1, original->LockDownConfigGlobalSmi, params->LockDownConfigGlobalSmi); @@ -674,190 +594,127 @@ original->SerialIrqConfigStartFramePulse, params->SerialIrqConfigStartFramePulse);
- fsp_display_upd_value("Psi1Threshold[0]", 1, - original->Psi1Threshold[0], + fsp_display_upd_value("Psi1Threshold[0]", 1, original->Psi1Threshold[0], params->Psi1Threshold[0]); - fsp_display_upd_value("Psi1Threshold[1]", 1, - original->Psi1Threshold[1], + fsp_display_upd_value("Psi1Threshold[1]", 1, original->Psi1Threshold[1], params->Psi1Threshold[1]); - fsp_display_upd_value("Psi1Threshold[2]", 1, - original->Psi1Threshold[2], + fsp_display_upd_value("Psi1Threshold[2]", 1, original->Psi1Threshold[2], params->Psi1Threshold[2]); - fsp_display_upd_value("Psi1Threshold[3]", 1, - original->Psi1Threshold[3], + fsp_display_upd_value("Psi1Threshold[3]", 1, original->Psi1Threshold[3], params->Psi1Threshold[3]); - fsp_display_upd_value("Psi1Threshold[4]", 1, - original->Psi1Threshold[4], + fsp_display_upd_value("Psi1Threshold[4]", 1, original->Psi1Threshold[4], params->Psi1Threshold[4]); - fsp_display_upd_value("Psi2Threshold[0]", 1, - original->Psi2Threshold[0], + fsp_display_upd_value("Psi2Threshold[0]", 1, original->Psi2Threshold[0], params->Psi2Threshold[0]); - fsp_display_upd_value("Psi2Threshold[1]", 1, - original->Psi2Threshold[1], + fsp_display_upd_value("Psi2Threshold[1]", 1, original->Psi2Threshold[1], params->Psi2Threshold[1]); - fsp_display_upd_value("Psi2Threshold[2]", 1, - original->Psi2Threshold[2], + fsp_display_upd_value("Psi2Threshold[2]", 1, original->Psi2Threshold[2], params->Psi2Threshold[2]); - fsp_display_upd_value("Psi2Threshold[3]", 1, - original->Psi2Threshold[3], + fsp_display_upd_value("Psi2Threshold[3]", 1, original->Psi2Threshold[3], params->Psi2Threshold[3]); - fsp_display_upd_value("Psi2Threshold[4]", 1, - original->Psi2Threshold[4], + fsp_display_upd_value("Psi2Threshold[4]", 1, original->Psi2Threshold[4], params->Psi2Threshold[4]); - fsp_display_upd_value("Psi3Threshold[0]", 1, - original->Psi3Threshold[0], + fsp_display_upd_value("Psi3Threshold[0]", 1, original->Psi3Threshold[0], params->Psi3Threshold[0]); - fsp_display_upd_value("Psi3Threshold[1]", 1, - original->Psi3Threshold[1], + fsp_display_upd_value("Psi3Threshold[1]", 1, original->Psi3Threshold[1], params->Psi3Threshold[1]); - fsp_display_upd_value("Psi3Threshold[2]", 1, - original->Psi3Threshold[2], + fsp_display_upd_value("Psi3Threshold[2]", 1, original->Psi3Threshold[2], params->Psi3Threshold[2]); - fsp_display_upd_value("Psi3Threshold[3]", 1, - original->Psi3Threshold[3], + fsp_display_upd_value("Psi3Threshold[3]", 1, original->Psi3Threshold[3], params->Psi3Threshold[3]); - fsp_display_upd_value("Psi3Threshold[4]", 1, - original->Psi3Threshold[4], + fsp_display_upd_value("Psi3Threshold[4]", 1, original->Psi3Threshold[4], params->Psi3Threshold[4]); - fsp_display_upd_value("Psi3Enable[0]", 1, - original->Psi3Enable[0], + fsp_display_upd_value("Psi3Enable[0]", 1, original->Psi3Enable[0], params->Psi3Enable[0]); - fsp_display_upd_value("Psi3Enable[1]", 1, - original->Psi3Enable[1], + fsp_display_upd_value("Psi3Enable[1]", 1, original->Psi3Enable[1], params->Psi3Enable[1]); - fsp_display_upd_value("Psi3Enable[2]", 1, - original->Psi3Enable[2], + fsp_display_upd_value("Psi3Enable[2]", 1, original->Psi3Enable[2], params->Psi3Enable[2]); - fsp_display_upd_value("Psi3Enable[3]", 1, - original->Psi3Enable[3], + fsp_display_upd_value("Psi3Enable[3]", 1, original->Psi3Enable[3], params->Psi3Enable[3]); - fsp_display_upd_value("Psi3Enable[4]", 1, - original->Psi3Enable[4], + fsp_display_upd_value("Psi3Enable[4]", 1, original->Psi3Enable[4], params->Psi3Enable[4]); - fsp_display_upd_value("Psi4Enable[0]", 1, - original->Psi4Enable[0], + fsp_display_upd_value("Psi4Enable[0]", 1, original->Psi4Enable[0], params->Psi4Enable[0]); - fsp_display_upd_value("Psi4Enable[1]", 1, - original->Psi4Enable[1], + fsp_display_upd_value("Psi4Enable[1]", 1, original->Psi4Enable[1], params->Psi4Enable[1]); - fsp_display_upd_value("Psi4Enable[2]", 1, - original->Psi4Enable[2], + fsp_display_upd_value("Psi4Enable[2]", 1, original->Psi4Enable[2], params->Psi4Enable[2]); - fsp_display_upd_value("Psi4Enable[3]", 1, - original->Psi4Enable[3], + fsp_display_upd_value("Psi4Enable[3]", 1, original->Psi4Enable[3], params->Psi4Enable[3]); - fsp_display_upd_value("Psi4Enable[4]", 1, - original->Psi4Enable[4], + fsp_display_upd_value("Psi4Enable[4]", 1, original->Psi4Enable[4], params->Psi4Enable[4]); - fsp_display_upd_value("ImonSlope[0]", 1, - original->ImonSlope[0], + fsp_display_upd_value("ImonSlope[0]", 1, original->ImonSlope[0], params->ImonSlope[0]); - fsp_display_upd_value("ImonSlope[1]", 1, - original->ImonSlope[1], + fsp_display_upd_value("ImonSlope[1]", 1, original->ImonSlope[1], params->ImonSlope[1]); - fsp_display_upd_value("ImonSlope[2]", 1, - original->ImonSlope[2], + fsp_display_upd_value("ImonSlope[2]", 1, original->ImonSlope[2], params->ImonSlope[2]); - fsp_display_upd_value("ImonSlope[3]", 1, - original->ImonSlope[3], + fsp_display_upd_value("ImonSlope[3]", 1, original->ImonSlope[3], params->ImonSlope[3]); - fsp_display_upd_value("ImonSlope[4]", 1, - original->ImonSlope[4], + fsp_display_upd_value("ImonSlope[4]", 1, original->ImonSlope[4], params->ImonSlope[4]); - fsp_display_upd_value("ImonOffse[0]t", 1, - original->ImonOffset[0], + fsp_display_upd_value("ImonOffse[0]t", 1, original->ImonOffset[0], params->ImonOffset[0]); - fsp_display_upd_value("ImonOffse[1]t", 1, - original->ImonOffset[1], + fsp_display_upd_value("ImonOffse[1]t", 1, original->ImonOffset[1], params->ImonOffset[1]); - fsp_display_upd_value("ImonOffse[2]t", 1, - original->ImonOffset[2], + fsp_display_upd_value("ImonOffse[2]t", 1, original->ImonOffset[2], params->ImonOffset[2]); - fsp_display_upd_value("ImonOffse[3]t", 1, - original->ImonOffset[3], + fsp_display_upd_value("ImonOffse[3]t", 1, original->ImonOffset[3], params->ImonOffset[3]); - fsp_display_upd_value("ImonOffse[4]t", 1, - original->ImonOffset[4], + fsp_display_upd_value("ImonOffse[4]t", 1, original->ImonOffset[4], params->ImonOffset[4]); - fsp_display_upd_value("IccMax[0]", 1, - original->IccMax[0], + fsp_display_upd_value("IccMax[0]", 1, original->IccMax[0], params->IccMax[0]); - fsp_display_upd_value("IccMax[1]", 1, - original->IccMax[1], + fsp_display_upd_value("IccMax[1]", 1, original->IccMax[1], params->IccMax[1]); - fsp_display_upd_value("IccMax[2]", 1, - original->IccMax[2], + fsp_display_upd_value("IccMax[2]", 1, original->IccMax[2], params->IccMax[2]); - fsp_display_upd_value("IccMax[3]", 1, - original->IccMax[3], + fsp_display_upd_value("IccMax[3]", 1, original->IccMax[3], params->IccMax[3]); - fsp_display_upd_value("IccMax[4]", 1, - original->IccMax[4], + fsp_display_upd_value("IccMax[4]", 1, original->IccMax[4], params->IccMax[4]); - fsp_display_upd_value("VrVoltageLimit[0]", 1, - original->VrVoltageLimit[0], + fsp_display_upd_value("VrVoltageLimit[0]", 1, original->VrVoltageLimit[0], params->VrVoltageLimit[0]); - fsp_display_upd_value("VrVoltageLimit[1]", 1, - original->VrVoltageLimit[1], + fsp_display_upd_value("VrVoltageLimit[1]", 1, original->VrVoltageLimit[1], params->VrVoltageLimit[1]); - fsp_display_upd_value("VrVoltageLimit[2]", 1, - original->VrVoltageLimit[2], + fsp_display_upd_value("VrVoltageLimit[2]", 1, original->VrVoltageLimit[2], params->VrVoltageLimit[2]); - fsp_display_upd_value("VrVoltageLimit[3]", 1, - original->VrVoltageLimit[3], + fsp_display_upd_value("VrVoltageLimit[3]", 1, original->VrVoltageLimit[3], params->VrVoltageLimit[3]); - fsp_display_upd_value("VrVoltageLimit[4]", 1, - original->VrVoltageLimit[4], + fsp_display_upd_value("VrVoltageLimit[4]", 1, original->VrVoltageLimit[4], params->VrVoltageLimit[4]); - fsp_display_upd_value("VrConfigEnable[0]", 1, - original->VrConfigEnable[0], + fsp_display_upd_value("VrConfigEnable[0]", 1, original->VrConfigEnable[0], params->VrConfigEnable[0]); - fsp_display_upd_value("VrConfigEnable[1]", 1, - original->VrConfigEnable[1], + fsp_display_upd_value("VrConfigEnable[1]", 1, original->VrConfigEnable[1], params->VrConfigEnable[1]); - fsp_display_upd_value("VrConfigEnable[2]", 1, - original->VrConfigEnable[2], + fsp_display_upd_value("VrConfigEnable[2]", 1, original->VrConfigEnable[2], params->VrConfigEnable[2]); - fsp_display_upd_value("VrConfigEnable[3]", 1, - original->VrConfigEnable[3], + fsp_display_upd_value("VrConfigEnable[3]", 1, original->VrConfigEnable[3], params->VrConfigEnable[3]); - fsp_display_upd_value("VrConfigEnable[4]", 1, - original->VrConfigEnable[4], + fsp_display_upd_value("VrConfigEnable[4]", 1, original->VrConfigEnable[4], params->VrConfigEnable[4]); - fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, - original->SerialIoI2cVoltage[0], + fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, original->SerialIoI2cVoltage[0], params->SerialIoI2cVoltage[0]); - fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, - original->SerialIoI2cVoltage[1], + fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, original->SerialIoI2cVoltage[1], params->SerialIoI2cVoltage[1]); - fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, - original->SerialIoI2cVoltage[2], + fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, original->SerialIoI2cVoltage[2], params->SerialIoI2cVoltage[2]); - fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, - original->SerialIoI2cVoltage[3], + fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, original->SerialIoI2cVoltage[3], params->SerialIoI2cVoltage[3]); - fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, - original->SerialIoI2cVoltage[4], + fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, original->SerialIoI2cVoltage[4], params->SerialIoI2cVoltage[4]); - fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, - original->SerialIoI2cVoltage[5], + fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5], params->SerialIoI2cVoltage[5]); - fsp_display_upd_value("SendVrMbxCmd", 1, - original->SendVrMbxCmd, - params->SendVrMbxCmd); - fsp_display_upd_value("AcousticNoiseMitigation", 1, - original->AcousticNoiseMitigation, + fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd); + fsp_display_upd_value("AcousticNoiseMitigation", 1, original->AcousticNoiseMitigation, params->AcousticNoiseMitigation); - fsp_display_upd_value("SlowSlewRateForIa", 1, - original->SlowSlewRateForIa, + fsp_display_upd_value("SlowSlewRateForIa", 1, original->SlowSlewRateForIa, params->SlowSlewRateForIa); - fsp_display_upd_value("SlowSlewRateForGt", 1, - original->SlowSlewRateForGt, + fsp_display_upd_value("SlowSlewRateForGt", 1, original->SlowSlewRateForGt, params->SlowSlewRateForGt); - fsp_display_upd_value("SlowSlewRateForSa", 1, - original->SlowSlewRateForSa, + fsp_display_upd_value("SlowSlewRateForSa", 1, original->SlowSlewRateForSa, params->SlowSlewRateForSa); - fsp_display_upd_value("FastPkgCRampDisable", 1, - original->FastPkgCRampDisable, + fsp_display_upd_value("FastPkgCRampDisable", 1, original->FastPkgCRampDisable, params->FastPkgCRampDisable); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1313dc1..1dbe590 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -142,8 +142,7 @@
/* * The following fields come from FspUpdVpd.h. - * These are configuration values that are passed to FSP during - * MemoryInit. + * These are configuration values that are passed to FSP during MemoryInit. */ u64 PlatformMemorySize; u8 SmramMask; @@ -191,9 +190,8 @@ /* SATA related */ u8 EnableSata; enum { - /* Documentation and header files of Skylake FSP disagree on - the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses - these: */ + /* Documentation and header files of Skylake FSP disagree on the values, + * Kaby Lake FSP (KabylakeFsp0001 on github) uses these: */ KBLFSP_SATA_MODE_AHCI = 0, KBLFSP_SATA_MODE_RAID = 1, } SataMode; @@ -224,8 +222,7 @@
/* * Pcie Root Port configuration: - * each element of array corresponds to - * respective PCIe root port. + * each element of array corresponds to respective PCIe root port. */
/* PEG Max Link Width */ @@ -361,8 +358,7 @@
/* * The following fields come from fsp_vpd.h - * These are configuration values that are passed to FSP during - * SiliconInit. + * These are configuration values that are passed to FSP during SiliconInit. */ u32 LogoPtr; u32 LogoSize; @@ -446,8 +442,7 @@ */ u8 PmConfigPciClockRun; /* - * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, - * 1: Enabled + * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled */ u8 PmConfigSlpStrchSusUp; /* @@ -481,8 +476,7 @@
/* * VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; /* diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..87bf644 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -86,14 +86,11 @@ };
/* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. + * If the PCIe root port at function 0 is disabled, the PCIe root ports might be coalesced + * after FSP silicon init. The below function will swap the devfn of the first enabled device + * in devicetree and function 0 resides a pci device so that it won't confuse coreboot. */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) +static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, size_t pci_groups) { struct device *func0; unsigned int devfn, devfn0; @@ -117,18 +114,13 @@ * Then find first enabled device to replace func0 * as that port was move to func0. */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { + for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { struct device *dev = pcidev_path_on_root(devfn); if (dev == NULL || !dev->enabled) continue;
- /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); + /* Found the first enabled device in a given dev number. */ + printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i); func0->path.pci.devfn = dev->path.pci.devfn; dev->path.pci.devfn = devfn0; break; @@ -160,8 +152,7 @@ pcie_update_device_tree(&pcie_table_skl_pch_h[0], ARRAY_SIZE(pcie_table_skl_pch_h)); } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); + printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x is not found\n", id); return; } } @@ -250,18 +241,12 @@ params->GraphicsConfigPtr = (u32) vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; }
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -269,8 +254,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -287,23 +271,20 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug));
/* - * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for - * all the enabled PCIe root ports, invalid(0x1F) is set for - * disabled PCIe root ports. + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for all the enabled + * PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. */ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { if (config->PcieRpClkReqSupport[i]) - params->PcieRpClkSrcNumber[i] = - config->PcieRpClkSrcNumber[i]; + params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i]; else params->PcieRpClkSrcNumber[i] = 0x1F; } @@ -344,12 +325,9 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled;
if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; + params->PchScsEmmcHs400DllDataValid = !!config->EmmcHs400DllNeed; + params->PchScsEmmcHs400RxStrobeDll1 = config->ScsEmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = config->ScsEmmcHs400TxDataDll; }
/* If ISH is enabled, enable ISH elements */ @@ -373,9 +351,8 @@ tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; /* - * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in FSP, + * To disable HECI, the Psf needs to be left unlocked by FSP till end of post sequence. + * Based on the devicetree setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; @@ -384,7 +361,7 @@ params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* - * Skip Spi Flash Lockdown from inside FSP. + * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). * So, it becomes coreboot's responsibility to set this bit @@ -413,8 +390,7 @@ params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PchPmPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur;
/* Indicate whether platform supports Voltage Margining */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..c551df8 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -151,8 +151,7 @@
/* Set long term power limit to TDP */ limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? tdp : (conf->tdp_pl1_override * power_unit)); limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
/* Set PL1 Pkg Power clamp bit */ @@ -182,10 +181,8 @@ if (conf->tdp_psyspl2) { limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", conf->tdp_psyspl2); + limit.hi |= (conf->tdp_psyspl2 * power_unit) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN;
@@ -196,20 +193,16 @@ if (conf->tdp_psyspl3) { limit = rdmsr(MSR_PL3_CONTROL); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & PKG_POWER_LIMIT_MASK; /* Enable PsysPl3 */ limit.lo |= PKG_POWER_LIMIT_EN; /* set PsysPl3 time window */ limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; + PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; /* set PsysPl3 duty cycle */ limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + PKG_POWER_LIMIT_DUTYCYCLE_MASK) << PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; wrmsr(MSR_PL3_CONTROL, limit); }
@@ -217,10 +210,8 @@ if (conf->tdp_pl4) { limit = rdmsr(MSR_VR_CURRENT_CONFIG); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & PKG_POWER_LIMIT_MASK; wrmsr(MSR_VR_CURRENT_CONFIG, limit); }
@@ -382,20 +373,17 @@
/* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); }
@@ -410,8 +398,7 @@ /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; /* Set PM1 timer IO port and enable*/ @@ -424,9 +411,10 @@ void soc_core_init(struct device *cpu) { /* Clear out pending MCEs */ - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some of these + * banks are core vs package scope. For now every CPU clears every bank. + */ mca_configure();
/* Enable the local CPU apics */ @@ -481,10 +469,7 @@ /* Set Max Ratio */ cpu_set_max_ratio();
- /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ + /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ smm_southbridge_enable(GBL_EN);
/* Lock down the SMRAM space. */ @@ -503,9 +488,8 @@
static const struct mp_ops mp_ops = { /* - * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, - * that are set prior to ramstage. - * Real MTRRs programming are being done after resource allocation. + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, that are set + * prior to ramstage. Real MTRRs programming are being done after resource allocation. */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, @@ -545,8 +529,7 @@ if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else - return (msr1.lo & PRMRR_SUPPORTED) && - (current_patch_id == new_patch_id - 1); + return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); }
void cpu_lock_sgx_memory(void) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..2bf9c52 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -52,19 +52,13 @@ #define PME_STS_BIT (1 << 15)
#ifdef __SIMPLE_DEVICE__ -static void pch_log_add_elog_event(const struct pme_status_info *info, - pci_devfn_t dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, pci_devfn_t dev) #else -static void pch_log_add_elog_event(const struct pme_status_info *info, - struct device *dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, struct device *dev) #endif { - /* - * If wake source is XHCI, check for detailed wake source events on - * USB2/3 ports. - */ - if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + /* If wake source is XHCI, check for detailed wake source events on USB2/3 ports. */ + if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return;
elog_add_event_wake(info->elog_event, 0); @@ -105,11 +99,10 @@ }
/* - * If device is still not found, but the wake source is internal PME, - * try probing XHCI ports to see if any of the USB2/3 ports indicate - * that it was the wake source. This path would be taken in case of GSMI - * logging with S0ix where the pci_pm_resume_noirq runs and clears the - * PME_STS_BIT in controller register. + * If device is still not found, but the wake source is internal PME, try probing XHCI + * ports to see if any of the USB2/3 ports indicate that it was the wake source. This + * path would be taken in case of GSMI logging with S0ix where the pci_pm_resume_noirq + * runs and clears the PME_STS_BIT in controller register. */ if (!dev_found) dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); @@ -155,10 +148,7 @@ if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT)) continue;
- /* - * Linux kernel uses PME STS bit information. So do not clear - * this bit. - */ + /* Linux kernel uses PME STS bit information. So do not clear this bit. */ pch_log_add_elog_event(&pme_status_info[i], dev); } } @@ -234,8 +224,7 @@ }
/* TCO Timeout */ - if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + if (ps->prev_sleep_state != ACPI_S3 && ps->tco2_sts & TCO_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ @@ -253,11 +242,9 @@ /* ACPI Wake Event */ if (ps->prev_sleep_state != ACPI_S0) { if (deep_sx) - elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, ps->prev_sleep_state); else - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); } }
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8afaf4d..633c347 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -79,8 +79,7 @@ config = config_of(dev);
/* - * Set low maximum temp value used for dynamic thermal sensor - * shutdown consideration. + * Set low maximum temp value used for dynamic thermal sensor shutdown consideration. * * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726..b5d5e33 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,12 +23,9 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .MicrocodeRegionBase = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, }, }; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..3a211ac 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -176,17 +176,14 @@ return routes; }
-uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, - int dw_reg, uint32_t reg_val) +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; - /* - * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 - * ~ GPP_F11. - */ + + /* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 ~ GPP_F11. */ if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1) reg_val = reg_val & ~(PAD_CFG1_TOL_1V8); - return reg_val;
+ return reg_val; } diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c06893e..fae6469 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -63,11 +63,10 @@ write32(base + PCH_PP_DIVISOR, reg32);
/* So far all devices seem to use the PCH PWM function. - The CPU PWM registers are all zero after reset. */ + The CPU PWM registers are all zero after reset. */ if (conf->gpu_pch_backlight_pwm_hz) { - /* Reference clock is 24MHz. We can choose either a 16 - or a 128 step increment. Use 16 if we would have less - than 100 steps otherwise. */ + /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. + * Use 16 if we would have less than 100 steps otherwise. */ const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken1; @@ -82,15 +81,12 @@ } write32(base + SOUTH_CHICKEN1, south_chicken1);
- pwm_period = 24 * 1000 * 1000 / pwm_increment - / conf->gpu_pch_backlight_pwm_hz; + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; /* Start with a 50% duty cycle. */ - write32(base + BLC_PWM_PCH_CTL2, - pwm_period << 16 | pwm_period / 2); + write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
write32(base + BLC_PWM_PCH_CTL1, - !!conf->gpu_pch_backlight_polarity << 29 | - BLM_PCH_PWM_ENABLE); + !!conf->gpu_pch_backlight_polarity << 29 | BLM_PCH_PWM_ENABLE); } }
@@ -101,9 +97,8 @@ graphics_setup_panel(dev);
/* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver does not execute. + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. This will allow the + * kernel to use 4-lane eDP links properly if the VBIOS or GOP driver does not execute. */ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { @@ -117,12 +112,9 @@ pci_write_config32(dev, PCI_COMMAND, reg32);
/* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. + * GFX PEIM module inside FSP binary is taking care of graphics initialization based on + * RUN_FSP_GOP Kconfig option and input VBT file. In case of non-FSP solution, SoC need + * to select another Kconfig to perform GFX initialization. */ if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ @@ -159,8 +151,8 @@ /* FIXME: Add platform specific mailbox initialization */ }
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, + struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index c39c066..f883ee5 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -30,9 +30,9 @@ unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); void southbridge_inject_dsdt(struct device *device); -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); -unsigned long northbridge_write_acpi_tables(struct device *, - unsigned long current, struct acpi_rsdp *); +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 0681f78..7455999 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -42,8 +42,7 @@ /* Common Timer Copy (CTC) frequency - 24MHz. */ #define CTC_FREQ 24000000
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 13a0a7a..3bfaba5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -18,8 +18,8 @@ #define _SOC_GPIO_H_
#include <soc/gpio_defs.h> -#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in - soc/gpio_defs.h */ +/* intelblocks/gpio.h depends on definitions in soc/gpio_defs.h */ +#include <intelblocks/gpio.h>
#define CROS_GPIO_DEVICE_NAME "INT344B:00" #endif diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..e012e3a 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -35,10 +35,8 @@ #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM3_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS)) + ((NUM_GPIO_COM0_GPI_REGS) + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) + (NUM_GPIO_COM2_GPI_REGS))
/* * IOxAPIC IRQs for the GPIOs @@ -220,9 +218,9 @@
/* Register defines. */ #define GPIO_MISCCFG 0x10 -#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 #define GPI_INT_STS_0 0x100 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c73d766..f1220de 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -22,8 +22,8 @@ /* * Memory-mapped I/O registers. */ -#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 -#define PCH_PRESERVED_BASE_SIZE 0x02000000 +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index a25e5ac..82de495 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -43,8 +43,8 @@ int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);
/* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 - * on error. + * Add nau88l25 headset codec on provided SSP link. + * Return 0 on succes, < 0 on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink);
@@ -72,8 +72,8 @@ int nhlt_soc_add_rt5514(struct nhlt *nhlt, int hwlink, int num_channels);
/* - * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add rt5663 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink);
@@ -84,8 +84,8 @@ int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink);
/* - * Add da7219 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add da7219 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink);
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 615edac..a220d8c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -145,8 +145,7 @@ * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ -#define ENABLE_SMI_PARAMS \ - (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) +#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0xac diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 88ce9e3..96faace 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -30,9 +30,8 @@ msr_t smrr_base; msr_t smrr_mask; /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE + * The smm_save_state_in_msrs field indicates if SMM save state locations live in MSRs. + * This indicates to the CPUs how to adjust the SMMBASE and IEDBASE */ int smm_save_state_in_msrs; }; diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index aebbbdf..2fa6f9f 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -27,15 +27,10 @@
struct vr_config {
- /* - * The below settings will take effect when this is set to 1 - * for that domain. - */ + /* The below settings will take effect when this is set to 1 for that domain. */ int vr_config_enable;
- /* Power State X current cutoff in 1/4 Amp increments - * Range is 0-128A - */ + /* Power State X current cutoff in 1/4 Amp increments Range is 0-128A */ int psi1threshold; int psi2threshold; int psi3threshold; @@ -45,8 +40,8 @@ int psi4enable;
/* - * Imon slope correction. Specified in 1/100 increment - * values. Range is 0-200. 125 = 1.25 + * Imon slope correction. Specified in 1/100 increment values. + * Range is 0-200. 125 = 1.25 */ int imon_slope;
@@ -72,8 +67,7 @@
#if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -85,8 +79,7 @@ }; #else /* VrConfig Settings for 4 domains - * 0 = System Agent, 1 = IA Core, - * 2 = GT unsliced, 3 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = GT unsliced, 3 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -97,6 +90,5 @@ }; #endif
-void fill_vr_domain_config(void *params, - int domain, const struct vr_config *cfg); +void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda..8ce0f78 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -24,198 +24,143 @@ #include <string.h>
static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { - /* - * cAVS(Audio, Voice, Speech), INTA is default, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), - /* - * SMBus Controller, no default value, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* cAVS(Audio, Voice, Speech), INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + + /* SMBus Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), - /* - * SerialIo: UART #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[7] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), - /* - * SerialIo: UART #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[8] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), - /* - * SerialIo: SPI #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[10] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), - /* - * SerialIo: SPI #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[11] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + + /* SerialIo: UART #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[7] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART0), int_A, + LPSS_UART0_IRQ), + + /* SerialIo: UART #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[8] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART1), int_B, + LPSS_UART1_IRQ), + + /* SerialIo: SPI #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[10] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI0), int_C, + LPSS_SPI0_IRQ), + + /* SerialIo: SPI #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[11] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI1), int_D, + LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), - /* PCI Express Port, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), - /* - * PCI Express Port 1, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), - /* - * PCI Express Port 2, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), - /* - * PCI Express Port 3, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), - /* - * PCI Express Port 4, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), - /* - * PCI Express Port 5, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), - /* - * PCI Express Port 6, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), - /* - * PCI Express Port 7, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), - /* - * PCI Express Port 8, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + + /* PCI Express Port, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + + /* PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + + /* PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + + /* PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + + /* PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + + /* PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + + /* PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + + /* PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + + /* PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* * SerialIo UART Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[9] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), /* * SerialIo UART Controller #5, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[6] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), /* * SerialIo UART Controller #4, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[5] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), - /* - * SATA Controller, INTA is default, - * programmed in PciCfgSpace + 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, - PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + + /* SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), /* * SerialIo I2C Controller #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[2] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), /* * SerialIo I2C Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[3] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), /* * SerialIo I2C Controller #3, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[4] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), - /* - * USB 3.0 xHCI Controller, no default value, - * programmed in PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + + /* USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + /* Camera IO Host Controller */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, - PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) };
void soc_irq_settings(FSP_SIL_UPD *params) @@ -229,9 +174,8 @@ /* Get Device Int Count */ intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) - (params->DevIntConfigPtr), devintconfig, intdeventry * - sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); + memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), + devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
params->NumOfDevIntConfig = intdeventry; /* PxRC to IRQ programming */ diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..b838c5c 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -93,38 +93,22 @@
/* HFSTS2[27:24] Power Management Event */ static const char *const me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = "CM0PG->CM0"
};
@@ -136,70 +120,41 @@
/* Progress Code 1 states */ static const char *const me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", + [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = "Set VSCC params", [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = "EFFS says ME disabled", [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", };
static void print_me_version(void *unused) @@ -258,8 +213,7 @@ */ heci_reset();
- if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, - HECI_MKHI_ADD)) + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, HECI_MKHI_ADD)) goto failed;
if (!heci_receive(&resp, &resp_size)) @@ -293,18 +247,14 @@ hfs3.data = me_read_config32(PCI_ME_HFSTS3); hfs6.data = me_read_config32(PCI_ME_HFSTS6);
- printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", - hfs.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", - hfs2.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", - hfs3.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", hfs.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", hfs2.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", hfs3.data); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 4 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS4)); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 5 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS5)); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", - hfs6.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", hfs6.data); /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs.fields.fpt_bad ? "BAD" : "OK"); @@ -344,12 +294,10 @@ printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2.fields.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_rom_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_rom_values) && me_progress_rom_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_rom_values[ - hfs2.fields.current_state]); + me_progress_rom_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -359,12 +307,10 @@ break;
case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_bup_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_bup_values) && me_progress_bup_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[ - hfs2.fields.current_state]); + me_progress_bup_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -417,8 +363,7 @@ printk(BIOS_DEBUG, "Corporate\n"); break; default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", - hfs3.fields.fw_sku); + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3.fields.fw_sku); } }
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a..acd5e92 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,8 +40,7 @@
static bool is_ptt_enable(void) { - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == PTT_PRESENT) return true;
return false; @@ -80,8 +79,7 @@ }
/* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) +static size_t get_prmrr_size(uintptr_t dram_base, const struct soc_intel_skylake_config *config) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; @@ -95,12 +93,10 @@ return 0;
/* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. + * PRMRR Sizes that are > 1MB and < 32MB are not supported and will fail out. */ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); + die("PRMRR Sizes that are > 1MB and < 32MB are not supported!\n");
prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index dd91435..7dd82fa 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -15,8 +15,7 @@
#include <soc/nhlt.h>
-/* The same DSP firmware settings are used for both the capture and - * render endpoints. */ +/* The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config nau88l25_formats[] = { /* 48 KHz 24-bits per sample. */ { diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index 9c48c7b..5be881c 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -53,8 +53,7 @@ { switch (num_channels) { case 4: - return nhlt_add_ssp_endpoints(nhlt, hwlink, - rt5514_4ch_descriptors, + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5514_4ch_descriptors, ARRAY_SIZE(rt5514_4ch_descriptors)); default: return -1; diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c5a3f53..a308265 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -16,8 +16,7 @@ #include <soc/nhlt.h>
/* - * The same DSP firmware settings are used for both the capture and - * render endpoints. + * The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config rt5663_formats[] = { /* 48 KHz 24-bits per sample. */ diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c index c1e9118..f118b38 100644 --- a/src/soc/intel/skylake/p2sb.c +++ b/src/soc/intel/skylake/p2sb.c @@ -31,14 +31,13 @@ * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband * access for MIPI controller. */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | - (1 << 16) | (1 << 10) | (1 << 1); + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | (1 << 16) | + (1 << 10) | (1 << 1);
ep_mask[P2SB_EP_MASK_5_REG] = mask;
/* - * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband - * access for XHCI controller. + * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband access for XHCI controller. */ mask = (1 << 6) | (1 << 5);
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe0605..65075ea 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -48,8 +48,7 @@ }
/* - * Set which power state system will be after reapplying - * the power (from G3 State) + * Set which power state system will be after reapplying the power (from G3 State) */ void pmc_soc_set_afterg3_en(const bool on) { @@ -84,10 +83,8 @@
static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ - REG_PCI_RMW16(GEN_PMCON_B, - ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), - S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | - DIS_SLP_X_STRCH_SUS_UP), + REG_PCI_RMW16(GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), + S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP), /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), REG_SCRIPT_END @@ -107,8 +104,7 @@ uint32_t reg; uint8_t *pmcbase = pmc_mmio_regs();
- printk(BIOS_DEBUG, "%sabling Deep S%c\n", - enable ? "En" : "Dis", sx + '0'); + printk(BIOS_DEBUG, "%sabling Deep S%c\n", enable ? "En" : "Dis", sx + '0'); reg = read32(pmcbase + offset); if (enable) reg |= mask; @@ -168,12 +164,10 @@ static void pm1_enable_pwrbtn_smi(void *unused) { /* - * Enable power button SMI only before jumping to payload. This ensures - * that: + * Enable power button SMI only before jumping to payload. This ensures that: * 1. Power button SMI is enabled only after coreboot is done. - * 2. On resume path, power button SMI is not enabled and thus avoids - * any shutdowns because of power button presses due to power button - * press in resume path. + * 2. On resume path, power button SMI is not enabled and thus avoids any shutdowns + * because of power button presses due to power button press in resume path. */ pmc_update_pm1_enable(PWRBTN_EN); } @@ -181,10 +175,9 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
/* - * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in - * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable - * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE# - * pin. + * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in deep_sx_config. + * If WAKE# pin is not enabled, then PCI Express Wake Disable bit needs to be set + * in PM1_EN to avoid unnecessary wakes caused by WAKE# pin. */ static void pm1_handle_wake_pin(void *unused) { diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b03..ee3c74d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -212,22 +212,18 @@ }
/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. + * Check for any power failure to determine if this a wake from S5 because + * the PCH does not set the WAK_STS bit when waking from a true G3 state. */ - if (!(ps->pm1_sts & WAK_STS) && - (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) + if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5;
/* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. + * If waking from S3 determine if deep S3 is enabled. If not, need to check both + * deep sleep well and normal suspend well. Otherwise just check deep sleep well. */ if (prev_sleep_state == ACPI_S3) { /* PWR_FLR represents deep sleep power well loss. */ @@ -250,8 +246,7 @@ ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS);
- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); @@ -260,8 +255,7 @@ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ff1a959..a87ce47 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -24,14 +24,12 @@ static void do_force_global_reset(void) { /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + * BIOS should ensure it does a global reset to reset both host and + * Intel ME by setting PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] */ pmc_global_reset_enable(true);
- /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ + /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */ do_full_reset(); }
@@ -39,7 +37,7 @@ { if (send_global_reset() != 0) { /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ + * force global reset using PMC CF9GR register */ do_force_global_reset(); } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2d0de2f..e1e3ad0 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -51,8 +51,7 @@ }
/* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { const struct soc_intel_skylake_config *config;
@@ -61,11 +60,10 @@ config = config_of_path(PCH_DEVFN_LPC);
/* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have access to + * the bios_reserved range so it always assumes 8MB is used and so the kernel will + * avoid the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB), + * there is not enough space for FBC to work with a high resolution panel. */ upd->IgdDvmt50PreAlloc = 2;
@@ -90,34 +88,25 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; }
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
- fsp_display_upd_value("PlatformMemorySize", 8, - old->PlatformMemorySize, new->PlatformMemorySize); - fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, - new->MemorySpdPtr00); - fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, - new->MemorySpdPtr01); - fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, - new->MemorySpdPtr10); - fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, - new->MemorySpdPtr11); + fsp_display_upd_value("PlatformMemorySize", 8, old->PlatformMemorySize, + new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, new->MemorySpdPtr11); fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, new->MemorySpdDataLen); fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], @@ -208,46 +197,32 @@ new->RcompResistor[1]); fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], new->RcompResistor[2]); - fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], - new->RcompTarget[0]); - fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], - new->RcompTarget[1]); - fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], - new->RcompTarget[2]); - fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], - new->RcompTarget[3]); - fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], - new->RcompTarget[4]); - fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, - new->CaVrefConfig); + fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], new->RcompTarget[4]); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, new->CaVrefConfig); fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); - fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, - new->MrcFastBoot); + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, new->MrcFastBoot); fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, - new->EnableTraceHub); + fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, new->IgdDvmt50PreAlloc); - fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, - new->InternalGfx); - fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, - new->ApertureSize); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); - fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, - new->FspCarBase); - fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, - new->FspCarSize); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, new->FspCarSize); }
/* SOC initialization after RAM is enabled. */ void soc_after_ram_init(struct romstage_params *params) { - /* Set the DISB as soon as possible after DRAM - * init and MRC cache is saved. - */ + /* Set the DISB as soon as possible after DRAM init and MRC cache is saved. */ pmc_set_disb(); }
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index ecd1428..c517d1f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -60,22 +60,16 @@ struct dimm_info *dest_dimm; struct memory_info *mem_info; const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID;
/* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = - fsp_find_extension_hob_by_guid(smbios_memory_info_guid, - &hob_size); + memory_info_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size); if (memory_info_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; }
- /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ + /* Allocate CBMEM area for DIMM information used to populate SMBIOS table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); if (mem_info == NULL) { printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); @@ -165,8 +159,7 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; }
-static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, - FSP_M_TEST_CONFIG *m_t_cfg, +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, FSP_M_TEST_CONFIG *m_t_cfg, const struct soc_intel_skylake_config *config) { const struct device *dev; @@ -177,8 +170,7 @@ * device pci 01.0 on end # enable PEG0 root port * device pci 01.1 off end # do not configure PEG1 * - * If PEG port is not defined in the device tree, it will be disabled - * in FSP + * If PEG port is not defined in the device tree, it will be disabled in FSP */ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) @@ -239,7 +231,7 @@ m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) - mask |= (1<<i); + mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask;
@@ -269,12 +261,11 @@ } else { m_cfg->InternalGfx = 1; /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake - * does not have access to the bios_reserved range so it always - * assumes 8MB is used and so the kernel will avoid the last - * 8MB of the stolen window. With the default stolen size of - * 32MB(-8MB) there is not enough space for FBC to work with - * a high resolution panel + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have + * access to the bios_reserved range so it always assumes 8MB is used and so + * the kernel will avoid the last 8MB of the stolen window. With the default + * stolen size of 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel. */ m_cfg->IgdDvmt50PreAlloc = 2; } @@ -324,14 +315,10 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..48884ec 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -33,8 +33,7 @@ if (config->ignore_vtd) return;
- const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); if (!vtd_capable) return;
@@ -58,11 +57,9 @@ };
/* Set Fixed MMIO address into PCI configuration space */ - sa_set_pci_bar(soc_fixed_pci_resources, - ARRAY_SIZE(soc_fixed_pci_resources)); + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); /* Set Fixed MMIO address into MCH base address */ - sa_set_mch_bar(soc_fixed_mch_resources, - ARRAY_SIZE(soc_fixed_mch_resources)); + sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources));
systemagent_vtd_init();
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..b4f16e9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,19 +27,15 @@
void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return;
/* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS + * BWE is RW, so the SMI was caused by a write to BWE, not by a write to the BIOS * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. + * This is the place where we notice someone is trying to tinker with the BIOS. + * We are trying to be nice and just ignore it. A more resolute answer would be + * to power down the box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); fast_spi_enable_wp(); @@ -48,8 +44,7 @@ /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void) { - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | + uint32_t sci_mask = SMI_HANDLER_SCI_EN(APM_STS_BIT) | SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
return sci_mask; diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..f92d3f4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -46,23 +46,20 @@ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); }
-static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, +static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase;
/* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. + * The relocated handler runs with all CPUs concurrently. Therefore stagger + * the entry points adjusting SMBASE downwards by save state size * CPU num. */ smbase = staggered_smbase; iedbase = relo_params->ied_base;
- printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", smbase, iedbase);
/* * All threads need to set IEDBASE and SMBASE to the relocated @@ -93,8 +90,7 @@ } else { em64t101_smm_state_save_area_t *save_state;
- save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -120,12 +116,10 @@ }
/* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. + * The relocation work is actually performed in SMM context, but the code resides in the + * ramstage module. This occurs by trampolining from the default SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; @@ -133,18 +127,15 @@ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. + * Determine if the processor supports saving state in MSRs. If so, enable it before + * the non-BSPs run so that SMM relocation can occur in parallel in the non-BSP CPUs. */ if (cpu == 0) { /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. + * If smm_save_state_in_msrs is 1 then that means this is the 2nd time through + * the relocation handler for the BSP. Parallel SMM handler relocation is + * taking place. However, it is desired to access other CPUs save state in the + * real SMM handler. Therefore, disable the SMM save state in MSRs feature. */ if (relo_params->smm_save_state_in_msrs) { msr_t smm_feature_control; @@ -154,10 +145,9 @@ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); } else if (bsp_setup_msr_save_state(relo_params)) /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. + * Just return from relocation handler if MSR save state is enabled. + * In that case the BSP will come back into the relocation handler + * to setup the new SMBASE as well disabling SMM save state in MSRs. */ return; } @@ -210,8 +200,7 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); }
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
@@ -243,10 +232,9 @@ void smm_relocate(void) { /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation shall take place. + * Run the relocation handler a second time on the BSP to do * the final move. + * For APs, a relocation handler always needs to be run. */ if (smm_reloc_params.smm_save_state_in_msrs) smm_initiate_relocation_parallel(); @@ -258,9 +246,8 @@ { struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. + * LOCK the SMM memory window and enable normal SMM. After running this + * function, only a full reset can make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f..825078b 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -30,23 +30,21 @@ bool soc_is_vtd_capable(void) { struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - return root_dev && - !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); + + return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); }
/* * SoC implementation * - * Add all known fixed memory ranges for Host Controller/Memory - * controller. + * Add all known fixed memory ranges for Host Controller/Memory controller. */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, @@ -60,11 +58,9 @@
if (!config->ignore_vtd && soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) - sa_add_fixed_mmio_resources(dev, index, - &soc_gfxvt_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1);
- sa_add_fixed_mmio_resources(dev, index, - &soc_vtvc0_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1); } }
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 089dd5d..7febe24 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -295,8 +295,7 @@ } #endif
-void fill_vr_domain_config(void *params, - int domain, const struct vr_config *chip_cfg) +void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; const struct vr_config *cfg;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35172
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Clean up ......................................................................
soc/intel/skylake: Clean up
Align things, reflow lines, tidy up comments and use SPDX headers.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains unchanged.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/gspi.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/da7219.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/spi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c 94 files changed, 1,493 insertions(+), 2,689 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35172/2/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/35172/2/src/soc/intel/skylake/bootb... PS2, Line 261: addr_decoder_common & 3, code indent should use tabs where possible
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35172
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Clean up ......................................................................
soc/intel/skylake: Clean up
Align things, reflow lines, tidy up comments and use SPDX headers.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains unchanged.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/gspi.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/da7219.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/spi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c 94 files changed, 1,493 insertions(+), 2,689 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35172/3/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/35172/3/src/soc/intel/skylake/bootb... PS3, Line 261: addr_decoder_common & 3, code indent should use tabs where possible
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35172
to look at the new patch set (#4).
Change subject: soc/intel/skylake: Clean up ......................................................................
soc/intel/skylake: Clean up
Align things, reflow lines, tidy up comments and use SPDX headers.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains unchanged.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/gspi.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/da7219.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/spi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c 94 files changed, 1,497 insertions(+), 2,693 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/4
Hello build bot (Jenkins), Patrick Georgi, Matt DeVillier, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35172
to look at the new patch set (#6).
Change subject: soc/intel/skylake: Clean up ......................................................................
soc/intel/skylake: Clean up
Align things, reflow lines, tidy up comments and use SPDX headers.
Tested with BUILD_TIMELESS=1, both Purism Librem 15 v4 and Google Lars result in identical binaries.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/gspi.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/da7219.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/spi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c 94 files changed, 1,497 insertions(+), 2,693 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/6
Hello build bot (Jenkins), Patrick Georgi, Matt DeVillier, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35172
to look at the new patch set (#7).
Change subject: soc/intel/skylake: Clean up ......................................................................
soc/intel/skylake: Clean up
Align things, reflow lines, tidy up comments and use SPDX headers.
Tested with BUILD_TIMELESS=1, using three different boards: - Purism Librem 15 v4 - Google Lars - Asrock H110M In all three cases, this change results in identical binaries.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/gspi.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/da7219.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/spi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c 94 files changed, 1,497 insertions(+), 2,693 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/7
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 7: Code-Review+2
(49 comments)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... File src/soc/intel/skylake/acpi.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 265: fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | hm, this will break from time to time when things get added and removed... what about putting each in a separate line?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 523: } newline?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 683: pm1_en |= PWRBTN_STS; newline
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 33: -- why not a single dash?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 110: uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 separate lines?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 7: #include <arch/acpi_device.h> : #include <device/i2c_simple.h> : #include <drivers/i2c/designware/dw_i2c.h> : #include <intelblocks/cfg.h> : #include <intelblocks/gspi.h> : #include <intelblocks/lpc_lib.h> : #include <stdint.h> : #include <soc/gpe.h> : #include <soc/gpio.h> : #include <soc/irq.h> : #include <soc/pci_devs.h> : #include <soc/pmc.h> : #include <soc/serialio.h> : #include <soc/usb.h> : #include <soc/vr_config.h> : #include <smbios.h> order
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 146: System Agent Geyserville maybe add a hint that this is SpeedStep?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 245: * 0: Disable Root Port : * 1: Enable Root Port : simply drop "Root Port"?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 252: * 0: Disable Clk-Req : * 1: Enable Clk-req : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 269: * 0: Disable AER : * 1: Enable AER : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 276: * 0: Disable LTR : * 1: Enable LTR : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 361: /* GPIO IRQ Route The valid values is 14 or 15*/ /* GPIO IRQ Route: valid values are 14 or 15 */
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 363: /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ /* SCI IRQ Select: valid values are 9, 10, 11, 20, 21, 22, 23 */
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 443: * Values 0: Disabled, 1: Enabled keep convention: each on a new line
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 447: /* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled */ same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 480: one space too much; each on a new line maybe?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 485: * HeciEnabled decides the state of HECI1 at end of boot : * Setting to 0 (default) disables HECI1 and hides the device from OS : missing dots
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 4: clude <bootmode.h> : #include <bootstate.h> : #include <cbmem.h> : #include <fsp/api.h> : #include <arch/acpi.h> : #include <console/console.h> : #include <device/device.h> : #include <device/pci_ids.h> : #include <fsp/util.h> order
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 192: r( space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 193: id( space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 265: tconfig->SataTestMode = config->SataTestMode; maybe move to line 258 to group sata stuff together?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 266: /* newline before
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c... PS7, Line 388: msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | : (ACPI_BASE_ADDRESS + PM1_TMR); : each on new line?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... PS7, Line 91: * we uc
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... File src/soc/intel/skylake/gpio.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... PS7, Line 54: : static const struct pad_community skl_gpio_communities[] = { : { : .port = PID_GPIOCOM0, : .first_pad = GPP_A0, : .last_pad = GPP_B23, : .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM0", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com0_groups, : .num_groups = ARRAY_SIZE(skl_community_com0_groups), : }, { : .port = PID_GPIOCOM1, : .first_pad = GPP_C0, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .last_pad = GPP_H23, : #else : .last_pad = GPP_E23, : #endif : .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM1", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com1_groups, : .num_groups = ARRAY_SIZE(skl_community_com1_groups), : }, { : .port = PID_GPIOCOM3, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .first_pad = GPP_I0, : .last_pad = GPP_I10, : #else : .first_pad = GPP_F0, : .last_pad = GPP_G7, : #endif : .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM3", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com3_groups, : .num_groups = ARRAY_SIZE(skl_community_com3_groups), : }, { : .port = PID_GPIOCOM2, : .first_pad = GPD0, : .last_pad = GPD11, : .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM2", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map_com2, : .num_reset_vals = ARRAY_SIZE(rst_map_com2), : .groups = skl_community_com2_groups, : .num_groups = ARRAY_SIZE(skl_community_com2_groups), : } : }; <3
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 30: one tab is enough
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/device_nvs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: #define SIO_NVS_I2C0 0 : #define SIO_NVS_I2C1 1 : #define SIO_NVS_I2C2 2 : #define SIO_NVS_I2C3 3 : #define SIO_NVS_I2C4 4 : #define SIO_NVS_I2C5 5 : #define SIO_NVS_SPI0 6 : #define SIO_NVS_SPI1 7 : #define SIO_NVS_UART0 8 : #define SIO_NVS_UART1 9 : #define SIO_NVS_UART2 10 : one tab
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: #define GPE0_DW0_00 0 : #define GPE0_DW0_01 1 : #define GPE0_DW0_02 2 : #define GPE0_DW0_03 3 : #define GPE0_DW0_04 4 : #define GPE0_DW0_05 5 : #define GPE0_DW0_06 6 : #define GPE0_DW0_07 7 : #define GPE0_DW0_08 8 : #define GPE0_DW0_09 9 : #define GPE0_DW0_10 10 : #define GPE0_DW0_11 11 : #define GPE0_DW0_12 12 : #define GPE0_DW0_13 13 : #define GPE0_DW0_14 14 : #define GPE0_DW0_15 15 : #define GPE0_DW0_16 16 : #define GPE0_DW0_17 17 : #define GPE0_DW0_18 18 : #define GPE0_DW0_19 19 : #define GPE0_DW0_20 20 : #define GPE0_DW0_21 21 : #define GPE0_DW0_22 22 : #define GPE0_DW0_23 23 : #define GPE0_DW0_24 24 : #define GPE0_DW0_25 25 : #define GPE0_DW0_26 26 : #define GPE0_DW0_27 27 : #define GPE0_DW0_28 28 : #define GPE0_DW0_29 29 : #define GPE0_DW0_30 30 : #define GPE0_DW0_31 31 : /* GPE_63_32 */ : #define GPE0_DW1_00 32 : #define GPE0_DW1_01 33 : #define GPE0_DW1_02 34 : #define GPE0_DW1_03 36 : #define GPE0_DW1_04 36 : #define GPE0_DW1_05 37 : #define GPE0_DW1_06 38 : #define GPE0_DW1_07 39 : #define GPE0_DW1_08 40 : #define GPE0_DW1_09 41 : #define GPE0_DW1_10 42 : #define GPE0_DW1_11 43 : #define GPE0_DW1_12 44 : #define GPE0_DW1_13 45 : #define GPE0_DW1_14 46 : #define GPE0_DW1_15 47 : #define GPE0_DW1_16 48 : #define GPE0_DW1_17 49 : #define GPE0_DW1_18 50 : #define GPE0_DW1_19 51 : #define GPE0_DW1_20 52 : #define GPE0_DW1_21 53 : #define GPE0_DW1_22 54 : #define GPE0_DW1_23 55 : #define GPE0_DW1_24 56 : #define GPE0_DW1_25 57 : #define GPE0_DW1_26 58 : #define GPE0_DW1_27 59 : #define GPE0_DW1_28 60 : #define GPE0_DW1_29 61 : #define GPE0_DW1_30 62 : #define GPE0_DW1_31 63 : /* GPE_95_64 */ : #define GPE0_DW2_00 64 : #define GPE0_DW2_01 65 : #define GPE0_DW2_02 66 : #define GPE0_DW2_03 67 : #define GPE0_DW2_04 68 : #define GPE0_DW2_05 69 : #define GPE0_DW2_06 70 : #define GPE0_DW2_07 71 : #define GPE0_DW2_08 72 : #define GPE0_DW2_09 73 : #define GPE0_DW2_10 74 : #define GPE0_DW2_11 75 : #define GPE0_DW2_12 76 : #define GPE0_DW2_13 77 : #define GPE0_DW2_14 78 : #define GPE0_DW2_15 79 : #define GPE0_DW2_16 80 : #define GPE0_DW2_17 81 : #define GPE0_DW2_18 82 : #define GPE0_DW2_19 83 : #define GPE0_DW2_20 84 : #define GPE0_DW2_21 85 : #define GPE0_DW2_22 86 : #define GPE0_DW2_23 87 : #define GPE0_DW2_24 88 : #define GPE0_DW2_25 89 : #define GPE0_DW2_26 90 : #define GPE0_DW2_27 91 : #define GPE0_DW2_28 92 : #define GPE0_DW2_29 93 : #define GPE0_DW2_30 94 : #define GPE0_DW2_31 95 : /* GPE_STD */ : #define GPE0_HOT_PLUG 97 : #define GPE0_SWGPE 98 : #define GPE0_TCOSCI 102 : #define GPE0_SMB_WAK 103 : #define GPE0_PCI_EXP 105 : #define GPE0_BATLOW 106 : #define GPE0_PME 107 : #define GPE0_ME_SCI 108 : #define GPE0_PME_B0 109 : #define GPE0_ESPI 110 : #define GPE0_GPIO_T2 111 : #define GPE0_LAN_WAK 112 : #define GPE0_WADT 114 : : #define GPE_MAX GPE0_WADT : one tab?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 210: GPIO_MISCCFG 0x10 : #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 : #define HOSTSW_OWN_REG_0 0xd0 : #define PAD_CFG_BASE 0x400 : #define GPI_INT_STS_0 0x100 : #define GPI_INT_EN_0 0x120 : #define GPI_SMI_STS_0 0x180 : #define GPI_SMI_EN_0 0x1a0 aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 12: e PCH_PRESERVED_BASE_ADDRESS 0xfc800000 : #define PCH_PRESERVED_BASE_SIZE 0x02000000 alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/irq.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 6: : #define GPIO_IRQ14 14 : #define GPIO_IRQ15 15 : : #define PCH_IRQ10 10 : #define PCH_IRQ11 11 : : #define SCI_IRQ9 9 : #define SCI_IRQ10 10 : #define SCI_IRQ11 11 : #define SCI_IRQ20 20 : #define SCI_IRQ21 21 : #define SCI_IRQ22 22 : #define SCI_IRQ23 23 : : #define TCO_IRQ9 9 : #define TCO_IRQ10 10 : #define TCO_IRQ11 11 : #define TCO_IRQ20 20 : #define TCO_IRQ21 21 : #define TCO_IRQ22 22 : #define TCO_IRQ23 23 : : #define LPSS_I2C0_IRQ 16 : #define LPSS_I2C1_IRQ 17 : #define LPSS_I2C2_IRQ 18 : #define LPSS_I2C3_IRQ 19 : #define LPSS_I2C4_IRQ 34 : #define LPSS_I2C5_IRQ 33 : #define LPSS_SPI0_IRQ 22 : #define LPSS_SPI1_IRQ 23 : #define LPSS_UART0_IRQ 20 : #define LPSS_UART1_IRQ 21 : #define LPSS_UART2_IRQ 32 : #define SDIO_IRQ 22 : : #define cAVS_INTA_IRQ 16 : #define SMBUS_INTA_IRQ 16 : #define SMBUS_INTB_IRQ 17 : #define GbE_INTA_IRQ 16 : #define GbE_INTC_IRQ 18 : #define TRACE_HUB_INTA_IRQ 16 : #define TRACE_HUB_INTD_IRQ 19 : : #define eMMC_IRQ 21 : #define SD_IRQ 23 : : #define PCIE_1_IRQ 16 : #define PCIE_2_IRQ 17 : #define PCIE_3_IRQ 18 : #define PCIE_4_IRQ 19 : #define PCIE_5_IRQ 16 : #define PCIE_6_IRQ 17 : #define PCIE_7_IRQ 18 : #define PCIE_8_IRQ 19 : #define PCIE_9_IRQ 16 : #define PCIE_10_IRQ 17 : #define PCIE_11_IRQ 18 : #define PCIE_12_IRQ 19 : : #define SATA_IRQ 16 : : #define HECI_1_IRQ 16 : #define HECI_2_IRQ 17 : #define IDER_IRQ 18 : #define KT_IRQ 19 : #define HECI_3_IRQ 16 : : #define XHCI_IRQ 16 : #define OTG_IRQ 17 : #define THERMAL_IRQ 18 : #define CIO_INTA_IRQ 16 : #define CIO_INTD_IRQ 19 : #define ISH_IRQ 20 : : #define PEG_RP_INTA_IRQ 16 : #define PEG_RP_INTB_IRQ 17 : #define PEG_RP_INTC_IRQ 18 : #define PEG_RP_INTD_IRQ 19 : : #define IGFX_IRQ 16 : #define SA_THERMAL_IRQ 16 : #define SKYCAM_IRQ 16 : #define GMM_IRQ 16 aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/me.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 37: #define ME_HFS2_PHASE_ROM 0 : #define ME_HFS2_PHASE_UKERNEL 2 : #define ME_HFS2_PHASE_BUP 3 : #define ME_HFS2_PHASE_HOST_COMM 6 : /* Current State - Based on Infra Progress values. */ : /* ROM State */ : #define ME_HFS2_STATE_ROM_BEGIN 0 : #define ME_HFS2_STATE_ROM_DISABLE 6 : /* BUP State */ : #define ME_HFS2_STATE_BUP_INIT 0 : #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 : #define ME_HFS2_STATE_BUP_CG_ENABLE 2 : #define ME_HFS2_STATE_BUP_PM_HND_EN 3 : #define ME_HFS2_STATE_BUP_FLOW_DET 4 : #define ME_HFS2_STATE_BUP_PMC_PATCHING 5 : #define ME_HFS2_STATE_BUP_GET_FLASH_VSCC 6 : #define ME_HFS2_STATE_BUP_SET_FLASH_VSCC 7 : #define ME_HFS2_STATE_BUP_VSCC_ERR 8 : #define ME_HFS2_STATE_BUP_EFSS_INIT 9 : #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa : #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb : #define ME_HFS2_STATE_BUP_STRAP_DIS 0xc : #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd : #define ME_HFS2_STATE_BUP_M3 0x11 : #define ME_HFS2_STATE_BUP_M0 0x12 : #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 : #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 : #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 : #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 : #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c : #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f : #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 : #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 : #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 : #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 : #define ME_HFS2_STATE_BUP_M0_CLK 0x26 : #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 : #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 : #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 : /* Policy Module State */ : #define ME_HFS2_STATE_POLICY_ENTRY 0 : #define ME_HFS2_STATE_POLICY_RCVD_S3 3 : #define ME_HFS2_STATE_POLICY_RCVD_S4 4 : #define ME_HFS2_STATE_POLICY_RCVD_S5 5 : #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 : #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 : #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 : #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 : #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa : #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb : #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc : #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd : #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe : #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf : #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 : /* Current PM Event Values */ : #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 : #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 : #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 : #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 : #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 : #define ME_HFS2_PMEVENT_CM0_CM3 7 : #define ME_HFS2_PMEVENT_CM3_CM0 8 : #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb : #define ME_HFS2_PMEVENT_CMX_CMOFF 0xc : #define ME_HFS2_PMEVENT_CM0_CM0PG 0xd : #define ME_HFS2_PMEVENT_CM3_CM3PG 0xe : #define ME_HFS2_PMEVENT_CM0PG_CM0 0xf ugh. aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/nhlt.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: ID 0x8086 : #define NHLT_DID_DMIC 0xae20 : #define NHLT_DID_BT 0xae30 : #define NHLT_DID_SSP 0xae alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 10: 0x6c : #define PCH_P2SB_HBDF 0x70 : : #define PCH_P2SB_EPMASK0 0xB0 : : #define PCH_PWRM_ACPI_TMR_CTL 0xFC aligmnet
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 40: OCK (1 << 18) : #define ACPI_BASE_LOCK (1 << 17) : #define SUS_PWR_FLR (1 << 14) : #define WOL_EN_OVRD (1 << 13) : #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) : #define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10) : #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) : #define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) : #define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) : #define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) : #define HOST_RST_STS (1 << 9) o.O
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/smbus.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: 0x04 : #define TCO_TIMEOUT (1 << 3) : #define TCO2_STS 0x06 : #define TCO_STS_SECOND_TO (1 << 1) : #define TCO_INTRD_DET (1 << 0) : #define TCO1_CNT 0x08 : #define TCO_LOCK (1 << 12) : #define TCO_TMR_HLT (1 << 11) : #define TCO2_CNT 0x0A : #define TCO_INTRD_SEL_MASK (3 << 1) : #define TCO_INTRD_SEL_SMI (1 << 2) : #define TCO_INTRD_SEL_INT (1 << 1) one tab less is enough
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/da7219.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 54: huh?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/dmic.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 97: ARRAY_SIZE(dmic_2ch_descriptors)); : case 4: : return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, : ARRAY_SIZE(dmi instead of removing one tab, adding 2 spaces would be right I think
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98357.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 34: misaligned
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98373.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 83: nts(nhlt, hwlink, max98373_descriptors, : AR alignment was correct here
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 73: ARRAY this looks wrong
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98927.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 35: drop one space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 36: ile = "max9 alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 64: ARR no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/nau88l25.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: ARRA no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5514.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 14: drop one space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 45: AR no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5663.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: A no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/ssm4567.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 57: A no
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 7:
(42 comments)
I agree with some of these, but some others are just... I don't have a bike.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... File src/soc/intel/skylake/acpi.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 265: fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED |
hm, this will break from time to time when things get added and removed... […]
How exactly will this break? Just checked `git blame`, this statement has not been touched at all since it was copied from Broadwell five years ago [CB:10340]. At that time, the line length was 80 characters.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 523: }
newline?
The line with the brace already provides enough clearance
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 683: pm1_en |= PWRBTN_STS;
newline
Where? I don't think it's necessary
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 33: --
why not a single dash?
Uh, I forgot this isn't Ada.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 110: uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66
separate lines?
Why?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 146: System Agent Geyserville
maybe add a hint that this is SpeedStep?
It is not, though.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 365: 3*/ space is missing
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 368: t.* space is missing
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 443: * Values 0: Disabled, 1: Enabled
keep convention: each on a new line
There isn't a convention, though. Neither before nor now.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 480:
one space too much; each on a new line maybe?
What's the value of NUM_VR_DOMAINS again?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 485: * HeciEnabled decides the state of HECI1 at end of boot : * Setting to 0 (default) disables HECI1 and hides the device from OS :
missing dots
Where?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 4: clude <bootmode.h> : #include <bootstate.h> : #include <cbmem.h> : #include <fsp/api.h> : #include <arch/acpi.h> : #include <console/console.h> : #include <device/device.h> : #include <device/pci_ids.h> : #include <fsp/util.h>
order
Out of scope. I can't easily tell whether reordering headers would result in the same binary in all cases.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 265: tconfig->SataTestMode = config->SataTestMode;
maybe move to line 258 to group sata stuff together?
Impossible to do in this change. Also, this is already grouped: see the first word of each line (`params` vs `tconfig`)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 266: /*
newline before
It's not too crammed, isn't it?
I might end up doing it, though, but only because I found a problem on the line right below...
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 267: Psf PSF
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c... PS7, Line 388: msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | : (ACPI_BASE_ADDRESS + PM1_TMR); :
each on new line?
Why?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... PS7, Line 91: * we
uc
What do you mean?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... File src/soc/intel/skylake/gpio.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... PS7, Line 54: : static const struct pad_community skl_gpio_communities[] = { : { : .port = PID_GPIOCOM0, : .first_pad = GPP_A0, : .last_pad = GPP_B23, : .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM0", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com0_groups, : .num_groups = ARRAY_SIZE(skl_community_com0_groups), : }, { : .port = PID_GPIOCOM1, : .first_pad = GPP_C0, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .last_pad = GPP_H23, : #else : .last_pad = GPP_E23, : #endif : .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM1", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com1_groups, : .num_groups = ARRAY_SIZE(skl_community_com1_groups), : }, { : .port = PID_GPIOCOM3, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .first_pad = GPP_I0, : .last_pad = GPP_I10, : #else : .first_pad = GPP_F0, : .last_pad = GPP_G7, : #endif : .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM3", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com3_groups, : .num_groups = ARRAY_SIZE(skl_community_com3_groups), : }, { : .port = PID_GPIOCOM2, : .first_pad = GPD0, : .last_pad = GPD11, : .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM2", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map_com2, : .num_reset_vals = ARRAY_SIZE(rst_map_com2), : .groups = skl_community_com2_groups, : .num_groups = ARRAY_SIZE(skl_community_com2_groups), : } : };
<3
I suffered.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 30:
one tab is enough
I guess
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/device_nvs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: #define SIO_NVS_I2C0 0 : #define SIO_NVS_I2C1 1 : #define SIO_NVS_I2C2 2 : #define SIO_NVS_I2C3 3 : #define SIO_NVS_I2C4 4 : #define SIO_NVS_I2C5 5 : #define SIO_NVS_SPI0 6 : #define SIO_NVS_SPI1 7 : #define SIO_NVS_UART0 8 : #define SIO_NVS_UART1 9 : #define SIO_NVS_UART2 10 :
one tab
That would bring the numbers too close to the device indices, and it confuses at least me.
What's there to align to one less tab, anyway?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: #define GPE0_DW0_00 0 : #define GPE0_DW0_01 1 : #define GPE0_DW0_02 2 : #define GPE0_DW0_03 3 : #define GPE0_DW0_04 4 : #define GPE0_DW0_05 5 : #define GPE0_DW0_06 6 : #define GPE0_DW0_07 7 : #define GPE0_DW0_08 8 : #define GPE0_DW0_09 9 : #define GPE0_DW0_10 10 : #define GPE0_DW0_11 11 : #define GPE0_DW0_12 12 : #define GPE0_DW0_13 13 : #define GPE0_DW0_14 14 : #define GPE0_DW0_15 15 : #define GPE0_DW0_16 16 : #define GPE0_DW0_17 17 : #define GPE0_DW0_18 18 : #define GPE0_DW0_19 19 : #define GPE0_DW0_20 20 : #define GPE0_DW0_21 21 : #define GPE0_DW0_22 22 : #define GPE0_DW0_23 23 : #define GPE0_DW0_24 24 : #define GPE0_DW0_25 25 : #define GPE0_DW0_26 26 : #define GPE0_DW0_27 27 : #define GPE0_DW0_28 28 : #define GPE0_DW0_29 29 : #define GPE0_DW0_30 30 : #define GPE0_DW0_31 31 : /* GPE_63_32 */ : #define GPE0_DW1_00 32 : #define GPE0_DW1_01 33 : #define GPE0_DW1_02 34 : #define GPE0_DW1_03 36 : #define GPE0_DW1_04 36 : #define GPE0_DW1_05 37 : #define GPE0_DW1_06 38 : #define GPE0_DW1_07 39 : #define GPE0_DW1_08 40 : #define GPE0_DW1_09 41 : #define GPE0_DW1_10 42 : #define GPE0_DW1_11 43 : #define GPE0_DW1_12 44 : #define GPE0_DW1_13 45 : #define GPE0_DW1_14 46 : #define GPE0_DW1_15 47 : #define GPE0_DW1_16 48 : #define GPE0_DW1_17 49 : #define GPE0_DW1_18 50 : #define GPE0_DW1_19 51 : #define GPE0_DW1_20 52 : #define GPE0_DW1_21 53 : #define GPE0_DW1_22 54 : #define GPE0_DW1_23 55 : #define GPE0_DW1_24 56 : #define GPE0_DW1_25 57 : #define GPE0_DW1_26 58 : #define GPE0_DW1_27 59 : #define GPE0_DW1_28 60 : #define GPE0_DW1_29 61 : #define GPE0_DW1_30 62 : #define GPE0_DW1_31 63 : /* GPE_95_64 */ : #define GPE0_DW2_00 64 : #define GPE0_DW2_01 65 : #define GPE0_DW2_02 66 : #define GPE0_DW2_03 67 : #define GPE0_DW2_04 68 : #define GPE0_DW2_05 69 : #define GPE0_DW2_06 70 : #define GPE0_DW2_07 71 : #define GPE0_DW2_08 72 : #define GPE0_DW2_09 73 : #define GPE0_DW2_10 74 : #define GPE0_DW2_11 75 : #define GPE0_DW2_12 76 : #define GPE0_DW2_13 77 : #define GPE0_DW2_14 78 : #define GPE0_DW2_15 79 : #define GPE0_DW2_16 80 : #define GPE0_DW2_17 81 : #define GPE0_DW2_18 82 : #define GPE0_DW2_19 83 : #define GPE0_DW2_20 84 : #define GPE0_DW2_21 85 : #define GPE0_DW2_22 86 : #define GPE0_DW2_23 87 : #define GPE0_DW2_24 88 : #define GPE0_DW2_25 89 : #define GPE0_DW2_26 90 : #define GPE0_DW2_27 91 : #define GPE0_DW2_28 92 : #define GPE0_DW2_29 93 : #define GPE0_DW2_30 94 : #define GPE0_DW2_31 95 : /* GPE_STD */ : #define GPE0_HOT_PLUG 97 : #define GPE0_SWGPE 98 : #define GPE0_TCOSCI 102 : #define GPE0_SMB_WAK 103 : #define GPE0_PCI_EXP 105 : #define GPE0_BATLOW 106 : #define GPE0_PME 107 : #define GPE0_ME_SCI 108 : #define GPE0_PME_B0 109 : #define GPE0_ESPI 110 : #define GPE0_GPIO_T2 111 : #define GPE0_LAN_WAK 112 : #define GPE0_WADT 114 : : #define GPE_MAX GPE0_WADT :
one tab?
See device_nvs.h
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 210: GPIO_MISCCFG 0x10 : #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 : #define HOSTSW_OWN_REG_0 0xd0 : #define PAD_CFG_BASE 0x400 : #define GPI_INT_STS_0 0x100 : #define GPI_INT_EN_0 0x120 : #define GPI_SMI_STS_0 0x180 : #define GPI_SMI_EN_0 0x1a0
aligment
It is aligned. Notice how `GPIO_DRIVER_IRQ_ROUTE_*` are not registers, but are related to fields within a register. It is only logical to have them stand out.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 12: e PCH_PRESERVED_BASE_ADDRESS 0xfc800000 : #define PCH_PRESERVED_BASE_SIZE 0x02000000
alignment
If line 16 can handle the extra tab, I'll do it
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/irq.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 6: : #define GPIO_IRQ14 14 : #define GPIO_IRQ15 15 : : #define PCH_IRQ10 10 : #define PCH_IRQ11 11 : : #define SCI_IRQ9 9 : #define SCI_IRQ10 10 : #define SCI_IRQ11 11 : #define SCI_IRQ20 20 : #define SCI_IRQ21 21 : #define SCI_IRQ22 22 : #define SCI_IRQ23 23 : : #define TCO_IRQ9 9 : #define TCO_IRQ10 10 : #define TCO_IRQ11 11 : #define TCO_IRQ20 20 : #define TCO_IRQ21 21 : #define TCO_IRQ22 22 : #define TCO_IRQ23 23 : : #define LPSS_I2C0_IRQ 16 : #define LPSS_I2C1_IRQ 17 : #define LPSS_I2C2_IRQ 18 : #define LPSS_I2C3_IRQ 19 : #define LPSS_I2C4_IRQ 34 : #define LPSS_I2C5_IRQ 33 : #define LPSS_SPI0_IRQ 22 : #define LPSS_SPI1_IRQ 23 : #define LPSS_UART0_IRQ 20 : #define LPSS_UART1_IRQ 21 : #define LPSS_UART2_IRQ 32 : #define SDIO_IRQ 22 : : #define cAVS_INTA_IRQ 16 : #define SMBUS_INTA_IRQ 16 : #define SMBUS_INTB_IRQ 17 : #define GbE_INTA_IRQ 16 : #define GbE_INTC_IRQ 18 : #define TRACE_HUB_INTA_IRQ 16 : #define TRACE_HUB_INTD_IRQ 19 : : #define eMMC_IRQ 21 : #define SD_IRQ 23 : : #define PCIE_1_IRQ 16 : #define PCIE_2_IRQ 17 : #define PCIE_3_IRQ 18 : #define PCIE_4_IRQ 19 : #define PCIE_5_IRQ 16 : #define PCIE_6_IRQ 17 : #define PCIE_7_IRQ 18 : #define PCIE_8_IRQ 19 : #define PCIE_9_IRQ 16 : #define PCIE_10_IRQ 17 : #define PCIE_11_IRQ 18 : #define PCIE_12_IRQ 19 : : #define SATA_IRQ 16 : : #define HECI_1_IRQ 16 : #define HECI_2_IRQ 17 : #define IDER_IRQ 18 : #define KT_IRQ 19 : #define HECI_3_IRQ 16 : : #define XHCI_IRQ 16 : #define OTG_IRQ 17 : #define THERMAL_IRQ 18 : #define CIO_INTA_IRQ 16 : #define CIO_INTD_IRQ 19 : #define ISH_IRQ 20 : : #define PEG_RP_INTA_IRQ 16 : #define PEG_RP_INTB_IRQ 17 : #define PEG_RP_INTC_IRQ 18 : #define PEG_RP_INTD_IRQ 19 : : #define IGFX_IRQ 16 : #define SA_THERMAL_IRQ 16 : #define SKYCAM_IRQ 16 : #define GMM_IRQ 16
aligment
Yes, I agree with you on this one.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/me.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 37: #define ME_HFS2_PHASE_ROM 0 : #define ME_HFS2_PHASE_UKERNEL 2 : #define ME_HFS2_PHASE_BUP 3 : #define ME_HFS2_PHASE_HOST_COMM 6 : /* Current State - Based on Infra Progress values. */ : /* ROM State */ : #define ME_HFS2_STATE_ROM_BEGIN 0 : #define ME_HFS2_STATE_ROM_DISABLE 6 : /* BUP State */ : #define ME_HFS2_STATE_BUP_INIT 0 : #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 : #define ME_HFS2_STATE_BUP_CG_ENABLE 2 : #define ME_HFS2_STATE_BUP_PM_HND_EN 3 : #define ME_HFS2_STATE_BUP_FLOW_DET 4 : #define ME_HFS2_STATE_BUP_PMC_PATCHING 5 : #define ME_HFS2_STATE_BUP_GET_FLASH_VSCC 6 : #define ME_HFS2_STATE_BUP_SET_FLASH_VSCC 7 : #define ME_HFS2_STATE_BUP_VSCC_ERR 8 : #define ME_HFS2_STATE_BUP_EFSS_INIT 9 : #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa : #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb : #define ME_HFS2_STATE_BUP_STRAP_DIS 0xc : #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd : #define ME_HFS2_STATE_BUP_M3 0x11 : #define ME_HFS2_STATE_BUP_M0 0x12 : #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 : #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 : #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 : #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 : #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c : #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f : #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 : #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 : #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 : #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 : #define ME_HFS2_STATE_BUP_M0_CLK 0x26 : #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 : #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 : #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 : /* Policy Module State */ : #define ME_HFS2_STATE_POLICY_ENTRY 0 : #define ME_HFS2_STATE_POLICY_RCVD_S3 3 : #define ME_HFS2_STATE_POLICY_RCVD_S4 4 : #define ME_HFS2_STATE_POLICY_RCVD_S5 5 : #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 : #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 : #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 : #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 : #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa : #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb : #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc : #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd : #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe : #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf : #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 : /* Current PM Event Values */ : #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 : #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 : #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 : #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 : #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 : #define ME_HFS2_PMEVENT_CM0_CM3 7 : #define ME_HFS2_PMEVENT_CM3_CM0 8 : #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb : #define ME_HFS2_PMEVENT_CMX_CMOFF 0xc : #define ME_HFS2_PMEVENT_CM0_CM0PG 0xd : #define ME_HFS2_PMEVENT_CM3_CM3PG 0xe : #define ME_HFS2_PMEVENT_CM0PG_CM0 0xf
ugh. […]
They are contiguous values. Maybe an enum would be better, but it's impossible to use an enum on this patch. I'll see if I can do anything.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/nhlt.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: ID 0x8086 : #define NHLT_DID_DMIC 0xae20 : #define NHLT_DID_BT 0xae30 : #define NHLT_DID_SSP 0xae
alignment
True, looks like a ball o'mud
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 10: 0x6c : #define PCH_P2SB_HBDF 0x70 : : #define PCH_P2SB_EPMASK0 0xB0 : : #define PCH_PWRM_ACPI_TMR_CTL 0xFC
aligmnet
True. The HPTC lines need a tab
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 40: OCK (1 << 18) : #define ACPI_BASE_LOCK (1 << 17) : #define SUS_PWR_FLR (1 << 14) : #define WOL_EN_OVRD (1 << 13) : #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) : #define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10) : #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) : #define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) : #define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) : #define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) : #define HOST_RST_STS (1 << 9)
o. […]
I'll see what I can do
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/smbus.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: 0x04 : #define TCO_TIMEOUT (1 << 3) : #define TCO2_STS 0x06 : #define TCO_STS_SECOND_TO (1 << 1) : #define TCO_INTRD_DET (1 << 0) : #define TCO1_CNT 0x08 : #define TCO_LOCK (1 << 12) : #define TCO_TMR_HLT (1 << 11) : #define TCO2_CNT 0x0A : #define TCO_INTRD_SEL_MASK (3 << 1) : #define TCO_INTRD_SEL_SMI (1 << 2) : #define TCO_INTRD_SEL_INT (1 << 1)
one tab less is enough
That would bring the values too close to the macro names.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/da7219.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 54:
huh?
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/dmic.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 97: ARRAY_SIZE(dmic_2ch_descriptors)); : case 4: : return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, : ARRAY_SIZE(dmi
instead of removing one tab, adding 2 spaces would be right I think
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98357.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 34:
misaligned
No. This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98373.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 83: nts(nhlt, hwlink, max98373_descriptors, : AR
alignment was correct here
See current patchset.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 73: ARRAY
this looks wrong
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98927.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 35:
drop one space
This is to align the central `|` character.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 36: ile = "max9
alignment
That one I forgot about
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 64: ARR
no
Yes. This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/nau88l25.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: ARRA
no
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5514.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 14:
drop one space
This is to align the central `|` character.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 45: AR
no
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5663.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: A
no
This is to align the array name on both lines, as it is the same.
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/ssm4567.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 57: A
no
This is to align the array name on both lines, as it is the same.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 146: System Agent Geyserville
It is not, though.
Well, it's related to EIST
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 7:
(10 comments)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... File src/soc/intel/skylake/acpi.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 265: fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED |
How exactly will this break? Just checked `git blame`, this statement has not been touched at all si […]
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 523: }
The line with the brace already provides enough clearance
a colon does, too. so why not drop all newlines^^ ;)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 683: pm1_en |= PWRBTN_STS;
Where? I don't think it's necessary
tbh it's personal preference, but with that argument you could also drop 686 and 697.. *shrugs*
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98927.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 35:
This is to align the central `|` character.
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 64: ARR
Yes. This is to align the array name on both lines, as it is the same.
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/nau88l25.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: ARRA
This is to align the array name on both lines, as it is the same.
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5514.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 14:
This is to align the central `|` character.
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 45: AR
This is to align the array name on both lines, as it is the same.
Ack
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5663.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: A
This is to align the array name on both lines, as it is the same.
Ack ... and ack to all the others. I was simply confused :)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/ssm4567.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 57: A
This is to align the array name on both lines, as it is the same.
Ack
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Abandoned
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