Change in coreboot[master]: soc/intel/{tigerlake, jasperlake}: Split Jasper Lake SoC code from Ti...

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39774 )

Change subject: soc/intel/{tigerlake, jasperlake}: Split Jasper Lake SoC code from Tiger Lake
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39774/5/src/soc/intel/jasperlake/in... 
File src/soc/intel/jasperlake/include/soc/romstage.h:

https://review.coreboot.org/c/coreboot/+/39774/5/src/soc/intel/jasperlake/in... 
PS5, Line 20: void mainboard_memory_init_params(FSPM_UPD *mupd);
need consistent spacing around '*' (ctx:WxV)