Change in ...coreboot[master]: buildsystem: Promote rules.h to default include - coreboot-gerrit

16 Jan 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/17656 )
Change subject: buildsystem: Promote rules.h to default include
......................................................................
buildsystem: Promote rules.h to default include
Does not fix 3rdparty/, *.S or *.ld or yet.
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) no-reply@coreboot.org
Reviewed-by: Nico Huber nico.h@gmx.de
---
M Makefile.inc
M src/arch/arm64/boot.c
M src/arch/riscv/boot.c
M src/arch/riscv/stages.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/exception.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/io.h
M src/arch/x86/include/arch/memlayout.h
M src/arch/x86/rdrand.c
M src/commonlib/storage/pci_sdhci.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/cpu/intel/microcode/microcode.c
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/pae/pgtbl.c
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/include/fsp/util.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/net/ne2k.c
M src/drivers/spi/spi_flash.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/device/device.h
M src/include/device/pci.h
M src/include/device/pnp.h
M src/include/memlayout.h
M src/include/stddef.h
M src/lib/bootmode.c
M src/lib/cbmem_common.c
M src/lib/ext_stage_cache.c
M src/lib/imd_cbmem.c
M src/lib/prog_loaders.c
M src/lib/romstage_handoff.c
M src/lib/timestamp.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/dragonegg/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/kahlee/ec.c
M src/mainboard/google/octopus/ec.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/reef/ec.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/storm/mmu.c
M src/mainboard/intel/cannonlake_rvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/strago/chromeos.c
M src/northbridge/intel/fsp_rangeley/northbridge.h
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/sandybridge/sandybridge.h
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_loader.c
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/intel/apollolake/include/soc/pci_devs.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/include/soc/iosf.h
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/braswell/include/soc/smm.h
M src/soc/intel/braswell/pmutil.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/braswell/tsc_freq.c
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/icelake/include/soc/pci_devs.h
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/skylake/include/soc/pch.h
M src/soc/intel/skylake/include/soc/pci_devs.h
M src/soc/intel/skylake/pmutil.c
M src/southbridge/amd/rs780/rs780.h
M src/southbridge/intel/bd82x6x/early_pch_common.c
98 files changed, 1 insertion(+), 97 deletions(-)
Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/Makefile.inc b/Makefile.inc
index ddebe5e..594ef36 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -383,6 +383,7 @@
 VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
+CPPFLAGS_common += -include $(src)/include/rules.h
 CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
 CPPFLAGS_common += -I3rdparty
 CPPFLAGS_common += -D__BUILD_DIR__="$(obj)"
diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index 54a33e0..c2119f3 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -19,7 +19,6 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <program_loading.h>
-#include <rules.h>
 #include <string.h>
static void run_payload(struct prog *prog)
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 04fba07..3d8d5d6 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -17,7 +17,6 @@
 #include <vm.h>
 #include <arch/boot.h>
 #include <arch/encoding.h>
-#include <rules.h>
 #include <console/console.h>
 #include <arch/smp/smp.h>
diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c
index 4fe0409..5e7fa4f 100644
--- a/src/arch/riscv/stages.c
+++ b/src/arch/riscv/stages.c
@@ -28,7 +28,6 @@
 #include <arch/encoding.h>
 #include <arch/stages.h>
 #include <arch/smp/smp.h>
-#include <rules.h>
void stage_entry(void)
 {
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ad9fe00..b5a9498 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -22,7 +22,6 @@
 #include <timestamp.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
-#include <rules.h>
 #include <symbols.h>
#if ENV_RAMSTAGE || ENV_POSTCAR
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 0f42fdf..700eb84 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -19,7 +19,6 @@
 #include <console/streams.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/lapic.h>
-#include <rules.h>
 #include <stdint.h>
 #include <string.h>
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index cd86e83..a061a27 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -57,7 +57,6 @@
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
 #include <stdint.h>
-#include <rules.h>
 #include <commonlib/helpers.h>
 #include <device/device.h>
 #include <uuid.h>
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index b50fef2..3ee5cea 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -16,7 +16,6 @@
#include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
/*
  * EFLAGS bits
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index 2cf76ad..2b74544 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -18,7 +18,6 @@
#include <arch/symbols.h>
 #include <stdlib.h>
-#include <rules.h>
#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
 asm(".section .car.global_data,"w",@nobits");
diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h
index 8f7213d..08aedef 100644
--- a/src/arch/x86/include/arch/exception.h
+++ b/src/arch/x86/include/arch/exception.h
@@ -31,7 +31,6 @@
 #define _ARCH_EXCEPTION_H
#include <arch/cpu.h>
-#include <rules.h>
#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
 asmlinkage void exception_init(void);
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index e4e3067..4050a47 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -16,7 +16,6 @@
#include <endian.h>
 #include <stdint.h>
-#include <rules.h>
 #include <device/pci_type.h>
/*
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 83e5b90..f93dece 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -16,7 +16,6 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
-#include <rules.h>
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
 /* No .data or .bss sections. Cache as RAM is handled separately. */
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
index 97aabd4..35aac71 100644
--- a/src/arch/x86/rdrand.c
+++ b/src/arch/x86/rdrand.c
@@ -14,7 +14,6 @@
  */
#include <random.h>
-#include <rules.h>
/*
  * Intel recommends that applications attempt 10 retries in a tight loop
diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
index 5ecd89b..9f7c521 100644
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #if ENV_RAMSTAGE
 #define __SIMPLE_DEVICE__		1
 #endif
diff --git a/src/console/console.c b/src/console/console.c
index 16c041e..1a6aec1 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -22,7 +22,6 @@
 #include <console/usb.h>
 #include <console/spi.h>
 #include <console/flash.h>
-#include <rules.h>
void console_hw_init(void)
 {
diff --git a/src/console/init.c b/src/console/init.c
index 0bafdbe..ff1d616 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -20,7 +20,6 @@
 #include <console/streams.h>
 #include <device/pci.h>
 #include <option.h>
-#include <rules.h>
 #include <version.h>
/* Mutable console log level only allowed when RAM comes online. */
diff --git a/src/console/post.c b/src/console/post.c
index 323a191..4c37535 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -20,7 +20,6 @@
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <smp/spinlock.h>
-#include <rules.h>
/* Write POST information */
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index d217cfd..abaeeb6 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -27,7 +27,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
-#include <rules.h>
#if !defined(__PRE_RAM__)
 #include <smp/spinlock.h>
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index ae7cc01..837bccf 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -15,7 +15,6 @@
#include <arch/rom_segs.h>
 #include <cpu/x86/post_code.h>
-#include <rules.h>
 #include <arch/x86/gdt_init.S>
.code32
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 2cc9ba6..278d50f 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -20,7 +20,6 @@
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/pae.h>
-#include <rules.h>
 #include <string.h>
 #include <symbols.h>
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 1671213..70e1ad7 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -24,7 +24,6 @@
  * performs the final stage of initialization.
  */
-#include <rules.h>
#define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index ffc43bc..0ad7a41 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -17,7 +17,6 @@
 #ifndef FSP1_1_UTIL_H
 #define FSP1_1_UTIL_H
-#include <rules.h>
 #include <fsp/api.h>
 /* Current users expect to get the SoC's FSP definitions by including util.h. */
 #include <fsp/soc_binding.h>
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index 6dbf2fb..e065924 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -13,7 +13,6 @@
 #ifndef _FSP2_0_INFO_HEADER_H_
 #define _FSP2_0_INFO_HEADER_H_
-#include <rules.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <types.h>
diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
index f56ab0d..caba600 100644
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@@ -34,7 +34,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <string.h>
 #include <ip_checksum.h>
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 57bdaf4..f06de2a 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -12,7 +12,6 @@
 #include <boot_device.h>
 #include <cpu/x86/smm.h>
 #include <delay.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <string.h>
 #include <spi-generic.h>
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index a61fbeb..9b5f57c 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <stdlib.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index b73a428..94a7fc9 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -19,7 +19,6 @@
 #include <console/uart.h>
 #include <device/device.h>
 #include <delay.h>
-#include <rules.h>
 #include <stdint.h>
 #include "uart8250reg.h"
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index edfabe5..420320e 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -15,7 +15,6 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
-#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index ad48e35..59f4e10 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -18,7 +18,6 @@
 #define _CBMEM_H_
#include <commonlib/cbmem_id.h>
-#include <rules.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <boot/coreboot_tables.h>
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
index e0e35b1..88e95bb 100644
--- a/src/include/console/cbmem_console.h
+++ b/src/include/console/cbmem_console.h
@@ -15,7 +15,6 @@
 #ifndef _CONSOLE_CBMEM_CONSOLE_H_
 #define _CONSOLE_CBMEM_CONSOLE_H_
-#include <rules.h>
 #include <stdint.h>
void cbmemc_init(void);
diff --git a/src/include/console/console.h b/src/include/console/console.h
index a5f7305..7ab61ea 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -17,7 +17,6 @@
 #define CONSOLE_CONSOLE_H_
#include <stdint.h>
-#include <rules.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
 #include <commonlib/loglevel.h>
diff --git a/src/include/console/flash.h b/src/include/console/flash.h
index 07bc724..1fd5f91 100644
--- a/src/include/console/flash.h
+++ b/src/include/console/flash.h
@@ -16,7 +16,6 @@
 #ifndef CONSOLE_FLASH_H
 #define CONSOLE_FLASH_H 1
-#include <rules.h>
 #include <stdint.h>
void flashconsole_init(void);
diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h
index 4b595e4..b52f566 100644
--- a/src/include/console/ne2k.h
+++ b/src/include/console/ne2k.h
@@ -16,7 +16,6 @@
 #ifndef _NE2K_H__
 #define _NE2K_H__
-#include <rules.h>
 #include <stdint.h>
void ne2k_append_data(unsigned char *d, int len, unsigned int base);
diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h
index 3175684..82dbd3f 100644
--- a/src/include/console/qemu_debugcon.h
+++ b/src/include/console/qemu_debugcon.h
@@ -1,7 +1,6 @@
 #ifndef _QEMU_DEBUGCON_H_
 #define _QEMU_DEBUGCON_H_
-#include <rules.h>
 #include <stdint.h>
void qemu_debugcon_init(void);
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
index 64379f8..dc88c9a 100644
--- a/src/include/console/spi.h
+++ b/src/include/console/spi.h
@@ -16,7 +16,6 @@
 #ifndef CONSOLE_SPI_H
 #define CONSOLE_SPI_H 1
-#include <rules.h>
 #include <stdint.h>
void spiconsole_init(void);
diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h
index 336cf14..f50aca3 100644
--- a/src/include/console/spkmodem.h
+++ b/src/include/console/spkmodem.h
@@ -1,7 +1,6 @@
 #ifndef SPKMODEM_H
 #define SPKMODEM_H 1
-#include <rules.h>
 #include <stdint.h>
void spkmodem_init(void);
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index 2e9c7b8..b074f35 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -16,7 +16,6 @@
 #ifndef CONSOLE_UART_H
 #define CONSOLE_UART_H
-#include <rules.h>
 #include <stdint.h>
/* Return the clock frequency UART uses as reference clock for
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index d58a6a6..4f10a5c 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -17,7 +17,6 @@
 #ifndef _CONSOLE_USB_H_
 #define _CONSOLE_USB_H_
-#include <rules.h>
 #include <stdint.h>
void usbdebug_init(void);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 540b7e3..c794322 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -11,7 +11,6 @@
#include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 #include <device/resource.h>
 #include <device/path.h>
 #include <device/pci_type.h>
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 7cf7e06..b750205 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -19,7 +19,6 @@
#include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/resource.h>
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index 69e0f8f..bc6391f 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -2,7 +2,6 @@
 #define DEVICE_PNP_H
#include <stdint.h>
-#include <rules.h>
 #include <device/device.h>
 #include <device/pnp_def.h>
 #include <arch/io.h>
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 5de2370..a8b3a60 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -18,7 +18,6 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
-#include <rules.h>
 #include <arch/memlayout.h>
/* Macros that the architecture can override. */
diff --git a/src/include/stddef.h b/src/include/stddef.h
index 5df7735..a82a68d 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -2,7 +2,6 @@
 #define STDDEF_H
#include <commonlib/helpers.h>
-#include <rules.h>
typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index dcee2d1..29682eb 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <bootmode.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c
index ba46609..4010494 100644
--- a/src/lib/cbmem_common.c
+++ b/src/lib/cbmem_common.c
@@ -15,7 +15,6 @@
#include <cbmem.h>
 #include <bootstate.h>
-#include <rules.h>
 #include <symbols.h>
void cbmem_run_init_hooks(int is_recovery)
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
index c3d4aee..354342d 100644
--- a/src/lib/ext_stage_cache.c
+++ b/src/lib/ext_stage_cache.c
@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <imd.h>
-#include <rules.h>
 #include <stage_cache.h>
 #include <string.h>
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index d6eed28..ff1cb95 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <imd.h>
-#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <arch/early_variables.h>
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index b763417..ac80a62 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -25,7 +25,6 @@
 #include <reset.h>
 #include <romstage_handoff.h>
 #include <rmodule.h>
-#include <rules.h>
 #include <stage_cache.h>
 #include <symbols.h>
 #include <timestamp.h>
diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c
index bdfdb64..04ead0a 100644
--- a/src/lib/romstage_handoff.c
+++ b/src/lib/romstage_handoff.c
@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
-#include <rules.h>
struct romstage_handoff {
    /* Indicate if the current boot is an S3 resume. If
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 36d0251..6885e7b 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -23,7 +23,6 @@
 #include <timer.h>
 #include <timestamp.h>
 #include <arch/early_variables.h>
-#include <rules.h>
 #include <smp/node.h>
#define MAX_TIMESTAMPS 192
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 7885642..fd403a7 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -15,7 +15,6 @@
  */
#include <arch/io.h>
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c
index fa388e5..657320c 100644
--- a/src/mainboard/google/dragonegg/chromeos.c
+++ b/src/mainboard/google/dragonegg/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c
index a77a23e..06a4de9 100644
--- a/src/mainboard/google/eve/chromeos.c
+++ b/src/mainboard/google/eve/chromeos.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c
index 066d0c3..3bd5b64 100644
--- a/src/mainboard/google/fizz/chromeos.c
+++ b/src/mainboard/google/fizz/chromeos.c
@@ -14,7 +14,6 @@
  */
#include <gpio.h>
-#include <rules.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
index 9433d7a..490ec00 100644
--- a/src/mainboard/google/glados/chromeos.c
+++ b/src/mainboard/google/glados/chromeos.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index d2933a6..7164591 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <rules.h>
 #include <soc/southbridge.h>
 #include <variant/ec.h>
diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c
index 8ed862c..afc241d 100644
--- a/src/mainboard/google/octopus/ec.c
+++ b/src/mainboard/google/octopus/ec.c
@@ -19,7 +19,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
static void ramstage_ec_init(void)
diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c
index cf9579e..83b8aa0 100644
--- a/src/mainboard/google/poppy/chromeos.c
+++ b/src/mainboard/google/poppy/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c
index e08889e..11d63ea 100644
--- a/src/mainboard/google/reef/ec.c
+++ b/src/mainboard/google/reef/ec.c
@@ -18,7 +18,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
static void ramstage_ec_init(void)
diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c
index 33647df..1e77cd9 100644
--- a/src/mainboard/google/sarien/chromeos.c
+++ b/src/mainboard/google/sarien/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c
index da15795..ba773c5 100644
--- a/src/mainboard/google/storm/mmu.c
+++ b/src/mainboard/google/storm/mmu.c
@@ -11,7 +11,6 @@
  */
#include <arch/cache.h>
-#include <rules.h>
 #include <soc/soc_services.h>
 #include <symbols.h>
 #include "mmu.h"
diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c
index b7dd91d..296a3a5 100644
--- a/src/mainboard/intel/cannonlake_rvp/chromeos.c
+++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c
index 9f7bc41..84f5f27 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos.c
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
index 09344a0..0138a9c 100644
--- a/src/mainboard/intel/glkrvp/ec.c
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -19,7 +19,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
static void ramstage_ec_init(void)
diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c
index 6fe27cd..5965d95 100644
--- a/src/mainboard/intel/icelake_rvp/chromeos.c
+++ b/src/mainboard/intel/icelake_rvp/chromeos.c
@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index e4afce2..2be3232 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -17,7 +17,6 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c
index 54f9bbe..75115c8 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.c
+++ b/src/mainboard/intel/kunimitsu/chromeos.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index fbcbcf7..5e9cad6 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
-#include <rules.h>
 #include <gpio.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index 11089a5..e384683 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -23,7 +23,6 @@
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
-#include <rules.h>
 #include <device/device.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 086afd5..736d6af 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -21,7 +21,6 @@
#ifndef __ACPI__
-#include <rules.h>
 #include <stdint.h>
typedef enum {
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 9e3da4b..8e6be29 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -65,7 +65,6 @@
    PLATFORM_DESKTOP_SERVER,
 };
-#include <rules.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */
diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c
index 24b8f95..59eaf2f 100644
--- a/src/security/vboot/bootmode.c
+++ b/src/security/vboot/bootmode.c
@@ -17,7 +17,6 @@
 #include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
-#include <rules.h>
 #include <string.h>
 #include <vb2_api.h>
 #include <security/vboot/misc.h>
diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c
index a8361ca..c80650f 100644
--- a/src/security/vboot/vboot_common.c
+++ b/src/security/vboot/vboot_common.c
@@ -20,7 +20,6 @@
 #include <fmap.h>
 #include <gbb_header.h>
 #include <reset.h>
-#include <rules.h>
 #include <stddef.h>
 #include <string.h>
 #include <security/vboot/gbb.h>
diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c
index 57a3b49..75f75b5 100644
--- a/src/security/vboot/vboot_loader.c
+++ b/src/security/vboot/vboot_loader.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <rmodule.h>
-#include <rules.h>
 #include <string.h>
 #include <security/vboot/misc.h>
 #include <security/vboot/symbols.h>
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index d376e6d..e12c8e9 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -20,7 +20,6 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <delay.h>
-#include <rules.h>
 #include <rmodule.h>
 #include <stage_cache.h>
 #include <string.h>
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index 038c071..20ab99b 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -17,7 +17,6 @@
 #define __PI_STONEYRIDGE_PCI_DEVS_H__
#include <device/pci_def.h>
-#include <rules.h>
#if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 7070d97..adf3af2 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <soc/iomap.h>
 #include "chip.h"
-#include <rules.h>
/*
  * AcpiMmio Region
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index ad726f8..5773a01 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -16,7 +16,6 @@
 #define _SOC_APOLLOLAKE_PCI_DEVS_H_
#include <device/pci_def.h>
-#include <rules.h>
#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 812a16a..e40f820 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -29,7 +29,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index efddc3b..44f1d3a 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -30,7 +30,6 @@
 #include <device/pci.h>
 #include <ec/google/chromeec/ec.h>
 #include <drivers/intel/gma/opregion.h>
-#include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>
 #include <soc/iomap.h>
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index 464f1cd..f02f07e 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -17,7 +17,6 @@
 #ifndef _SOC_IOSF_H_
 #define _SOC_IOSF_H_
-#include <rules.h>
 #include <stdint.h>
 #if ENV_RAMSTAGE
 #include <device/device.h>
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 7f044a5..d2dc706 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -19,7 +19,6 @@
 #define _SOC_NVS_H_
#include <commonlib/helpers.h>
-#include <rules.h>
 #include <soc/device_nvs.h>
 #include <vendorcode/google/chromeos/gnvs.h>
diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h
index 13b511a..93065a2 100644
--- a/src/soc/intel/braswell/include/soc/smm.h
+++ b/src/soc/intel/braswell/include/soc/smm.h
@@ -17,7 +17,6 @@
 #ifndef _SOC_SMM_H_
 #define _SOC_SMM_H_
-#include <rules.h>
#if ENV_RAMSTAGE
 #include <stdint.h>
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 8dbb499..be1b49e 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -18,7 +18,6 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 988832d..febf1d2 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -19,7 +19,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <delay.h>
-#include <rules.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <spi_flash.h>
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index 891aaff..28e3761 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -16,7 +16,6 @@
#include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <rules.h>
 #include <soc/msr.h>
 #if ENV_RAMSTAGE
 #include <soc/ramstage.h>
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 005cda3..779f1d0 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -18,7 +18,6 @@
 #define _SOC_CANNONLAKE_PCI_DEVS_H_
#include <device/pci_def.h>
-#include <rules.h>
#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index b57102d..6783b93 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -31,7 +31,6 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
 #include <halt.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index e93223f..f9930c1 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <intelblocks/p2sb.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index b10a905..3535862 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -20,7 +20,6 @@
/* All these devices live on bus 0 with the associated device and function */
-#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)
diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h
index 94f1d0d..13c56d6b 100644
--- a/src/soc/intel/icelake/include/soc/pci_devs.h
+++ b/src/soc/intel/icelake/include/soc/pci_devs.h
@@ -17,7 +17,6 @@
 #define _SOC_ICELAKE_PCI_DEVS_H_
#include <device/pci_def.h>
-#include <rules.h>
#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index abd52c4..2f08933 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -30,7 +30,6 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
 #include <halt.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 7102a78..72b1ac9 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -19,7 +19,6 @@
 #define _SOC_NVS_H_
#include <commonlib/helpers.h>
-#include <rules.h>
 #include <vendorcode/google/chromeos/gnvs.h>
typedef struct global_nvs_t {
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index e9e2f2f..d95bcaf 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -19,7 +19,6 @@
 #define _SOC_PCH_H_
#include <device/device.h>
-#include <rules.h>
void pch_log_state(void);
 #if ENV_RAMSTAGE
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 1fc3621..2f432a5 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -18,7 +18,6 @@
 #define _SOC_SKYLAKE_PCI_DEVS_H_
#include <device/pci_def.h>
-#include <rules.h>
#define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 335df53..a79cf04 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -29,7 +29,6 @@
 #include <halt.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/tco.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index 354555f..3a9dbee 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -16,7 +16,6 @@
 #ifndef __RS780_H__
 #define __RS780_H__
-#include <rules.h>
 #include <stdint.h>
 #include "chip.h"
 #include "rev.h"
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index a9ec9b1..2e9ad7f 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -20,7 +20,6 @@
 #include "pch.h"
 #include <arch/acpi.h>
 #include <console/console.h>
-#include <rules.h>
#if ENV_ROMSTAGE
 int southbridge_detect_s3_resume(void)
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Gerrit-Change-Number: 17656
Gerrit-PatchSet: 11
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
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