[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

[Felix Held (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email )

Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
......................................................................

Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81080/comment/70dd0b83_26c9a120 :
PS3, Line 839: 	if (CONFIG(SOC_ESPI)) {
> Oh, good point. Could tie it do 1f. […]

i'd guess that 1f.0 always needs to be enabled, since it's the primary function of that pci device. no idea about the external interface though.
would probably be good if an Intel engineer can help looking into this