Change in coreboot[master]: [NOTFORMERGE] cpu/x86/mtrr.h: ALIGN() fix

[Kyösti Mälkki (Code Review)]

Hello Nico Huber,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/41819

to review the following change.

Change subject: [NOTFORMERGE] cpu/x86/mtrr.h: ALIGN() fix
......................................................................

[NOTFORMERGE] cpu/x86/mtrr.h: ALIGN() fix

Duplicate of CB:41785

Change-Id: Ic9023eceaf86143cd64f89489ba796b0983d39e9
Signed-off-by: Kyösti Mälkki 
---
M src/include/cpu/x86/mtrr.h
1 file changed, 2 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41819/1

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 50148ff..301ea30 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -1,7 +1,6 @@
 #ifndef CPU_X86_MTRR_H
 #define CPU_X86_MTRR_H

-#include <commonlib/helpers.h>
 #ifndef __ASSEMBLER__
 #include <cpu/x86/msr.h>
 #include <arch/cpu.h>
@@ -187,8 +186,8 @@

/* Last but not least, most (if not all) chipsets have MMIO
    between 0xfe000000 and 0xff000000, so limit to 16MiB. */
-#if CAR_CACHE_ROM_SIZE >= 16 * MiB
-# define CACHE_ROM_SIZE (16 * MiB)
+#if CAR_CACHE_ROM_SIZE >= 16 << 20
+# define CACHE_ROM_SIZE (16 << 20)
 #else
 # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE
 #endif

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41819 )

Change subject: [NOTFORMERGE] cpu/x86/mtrr.h: ALIGN() fix
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Abandoned