Change in coreboot[master]: soc/intel/tigerlake: Fix build issues

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded a new patch set (#5) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 )

Change subject: soc/intel/tigerlake: Fix build issues
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soc/intel/tigerlake: Fix build issues

Add following to fix build issues:
  1. Update ASL files:
     a. Add new PMC, SMBUS files
     b. Remove unused files
     c. Update tigerlake specific changes on top of icelake
  2. Update tigerlake PMC_REG_BASE
  3. Update SOC header files to include tigerlake specific
  4. Update chip files to include tigerlake PCH DEVFNs

Signed-off-by: Ravi Sarawadi 
Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c
---
M src/soc/intel/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/acpi/northbridge.asl
A src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/acpi/pcie.asl
M src/soc/intel/tigerlake/acpi/platform.asl
A src/soc/intel/tigerlake/acpi/pmc.asl
D src/soc/intel/tigerlake/acpi/scs.asl
M src/soc/intel/tigerlake/acpi/serialio.asl
A src/soc/intel/tigerlake/acpi/sleepstates.asl
R src/soc/intel/tigerlake/acpi/smbus.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/irq.h
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/include/soc/pmc.h
M src/soc/intel/tigerlake/include/soc/ramstage.h
M src/soc/intel/tigerlake/include/soc/romstage.h
M src/soc/intel/tigerlake/include/soc/serialio.h
M src/soc/intel/tigerlake/pmutil.c
M src/soc/intel/tigerlake/romstage/fsp_params.c
26 files changed, 867 insertions(+), 457 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/5