Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43733 )
Change subject: nb/intel/ironlake: Correct PCIEXBAR definition ......................................................................
nb/intel/ironlake: Correct PCIEXBAR definition
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 4 files changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43733/1
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 1fa7267..c954086 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses;
- pciexbar_reg = pci_read_config32(QPI_SAD, 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 50e7adb..89eb813 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -6,6 +6,6 @@
void bootblock_early_northbridge_init(void) { - pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(QPI_SAD, 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index b835736..a681734 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -11,7 +11,6 @@ #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0)
-#define PCIEXBAR 0x60 #define DMIBAR 0x68
#define LAC 0x87 /* Legacy Access Control */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index dd8de97..afd3082 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -55,6 +55,8 @@ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
+#define SAD_PCIEXBAR 0x50 +
/* Device 0:2.0 PCI configuration space (Graphics Device) */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43733 )
Change subject: nb/intel/ironlake: Correct PCIEXBAR definition ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43733 )
Change subject: nb/intel/ironlake: Correct PCIEXBAR definition ......................................................................
nb/intel/ironlake: Correct PCIEXBAR definition
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 4 files changed, 5 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 1fa7267..c954086 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses;
- pciexbar_reg = pci_read_config32(QPI_SAD, 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 50e7adb..89eb813 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -6,6 +6,6 @@
void bootblock_early_northbridge_init(void) { - pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(QPI_SAD, 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index b835736..a681734 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -11,7 +11,6 @@ #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0)
-#define PCIEXBAR 0x60 #define DMIBAR 0x68
#define LAC 0x87 /* Legacy Access Control */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index dd8de97..afd3082 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -55,6 +55,8 @@ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
+#define SAD_PCIEXBAR 0x50 +
/* Device 0:2.0 PCI configuration space (Graphics Device) */
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Georgi (Code Review)