Patch merged into coreboot/master: c0c620e superiotool: add CR dump for W83627UHG = NCT6627UD

the following patch was just integrated into master:
commit c0c620e74ab4578ac8bd8ca80c7265fc4c62a37c
Author: Frank Rysanek 
Date:   Fri Apr 5 10:44:10 2013 +0200

superiotool: add CR dump for W83627UHG = NCT6627UD

This commit adds "register dump capability" to
    superiotool for a specific chip by Winbond/Nuvoton:
    the W83627UHG   AKA   NCT6627UD  (same chip, different package).
    In other words, it fills in the "CR map" definitions in winbond.c,
    which so far have been void for this chip.
    -
    superiotool r4.0-3976-g190011e
    Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e
    Register dump:
    idx 02 20 21 22 23 24 25 26  27 28 29 2a 2b 2c 2d 2e  2f
    val ff a2 32 ff f0 44 00 00  ff 00 00 00 00 03 00 00  ff
    def 00 a2 NA ff f0 MM 00 MM  RR 00 00 00 00 02 00 00  00
    LDN 0x00 (Floppy)
    idx 30 60 61 70 74 f0 f1 f2  f4 f5
    val 00 00 00 00 02 8e 00 ff  00 00
    def 01 03 f0 06 02 8e 00 ff  00 00
    LDN 0x01 (Parallel port)
    idx 30 60 61 70 74 f0
    val 00 03 78 0c 04 3f
    def 01 03 78 07 04 3f
    LDN 0x02 (UART A)
    idx 30 60 61 70 f0
    val 01 03 f8 04 00
    def 01 03 f8 04 00
    LDN 0x03 (UART B)
    idx 30 60 61 70 f0 f1
    val 01 02 f8 03 00 44
    def 01 02 f8 03 00 00
    LDN 0x05 (Keyboard)
    idx 30 60 61 62 63 70 72 f0
    val 01 00 60 00 64 01 0c 82
    def 01 00 60 00 64 01 0c 83
    LDN 0x06 (UART C)
    idx 30 60 61 70 f0
    val 01 03 e8 05 80
    def 01 03 e0 04 00
    LDN 0x07 (GPIO 3, GPIO 4)
    idx 30 e0 e1 e2 e3 e4 e5 e6  e7
    val 04 ff ff ff ff ff ff ff  ff
    def 00 ff 00 00 00 ff 00 00  00
    LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address)
    idx 30 60 61 e0 e1 e2 e3 e4  e5 e6 e7 f5 f6 f7
    val 01 00 00 ff ff ff ff ff  ff ff ff 02 00 00
    def 02 00 00 ff 00 00 00 ff  1f 00 00 00 00 00
    LDN 0x09 (GPIO 1, GPIO 2 and SUSLED)
    idx 30 e0 e1 e2 e3 e4 e5 e6  e7 f3
    val 02 ff ff ff ff 00 ff 00  00 00
    def 00 ff 00 00 00 ff 00 00  00 00
    LDN 0x0a (ACPI)
    idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 e9 f2 f3 f4 f6  f7 fe
    val 01 00 01 00 0a 00 00 00  0c 00 09 00 01 00 00 00  00 00
    def 00 00 01 00 ff 08 00 00  1c 00 RR RR 3e 00 00 00  00 00
    LDN 0x0b (Hardware monitor)
    idx 30 60 61 70 f0 f1 f2
    val 01 02 48 00 81 ff 81
    def 00 00 00 00 RR RR 00
    LDN 0x0c (PECI, SST)
    idx e0 e1 e2 e3 e4 e5 e6 e7  e8 f1 f2 f3 fe ff
    val 00 48 48 48 48 00 00 00  00 4c 50 10 23 5a
    def 00 48 48 48 48 00 RR RR  00 48 50 10 23 5a
    LDN 0x0d (UART D)
    idx 30 60 61 70 f0
    val 00 00 00 00 00
    def 00 02 e0 03 00
    LDN 0x0e (UART E)
    idx 30 60 61 70 f0
    val 00 00 00 00 80
    def 00 03 e8 04 00
    LDN 0x0f (UART F)
    idx 30 60 61 70 f0
    val 01 02 38 0a 00
    def 00 02 e8 03 00

Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56
    Signed-off-by: Frank Rysanek 
    Reviewed-on: http://review.coreboot.org/3027
    Reviewed-by: Paul Menzel 
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov

Build-Tested: build bot (Jenkins) at Fri Apr  5 13:22:55 2013, giving +1
Reviewed-By: Anton Kochkov  at Mon Apr 22 17:07:12 2013, giving +2
See http://review.coreboot.org/3027 for details.

-gerrit