Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53925 )

Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree
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soc/intel/skylake: Set proper defaults in chipset devicetree

LPC, P2SB and Power Management controller are always needed. Thus,
enable them by default.

Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Angel Pons 
Reviewed-by: Michael Niewöhner 
---
M src/soc/intel/skylake/chipset.cb
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
index 428db67..37100f0 100644
--- a/src/soc/intel/skylake/chipset.cb
+++ b/src/soc/intel/skylake/chipset.cb
@@ -59,9 +59,9 @@
    	device pci 1e.4 alias emmc         off end # EMMC
    	device pci 1e.5 alias sdio         off end # SDIO
    	device pci 1e.6 alias sdxc         off end # SDXC
-		device pci 1f.0 alias lpc_espi     off end # LPC Interface
-		device pci 1f.1 alias p2sb         off end # P2SB
-		device pci 1f.2 alias pmc          off end # Power Management Controller
+		device pci 1f.0 alias lpc_espi     on  end # LPC Interface
+		device pci 1f.1 alias p2sb         on  end # P2SB
+		device pci 1f.2 alias pmc          on  end # Power Management Controller
    	device pci 1f.3 alias hda          off end # Intel HDA
    	device pci 1f.4 alias smbus        off end # SMBus
    	device pci 1f.5 alias fast_spi     off end # PCH SPI