Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tuning I2C bus 1, 2 and 3 clock ......................................................................
mb/google/kahlee/treeya: Tuning I2C bus 1, 2 and 3 clock
Need tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock frequency less than 400KHz
Signed-off-by: Peichao.Wang peichao.wang@bitland.corp-partner.google.com Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35298/1
diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index beb99e0..2e25340 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -35,22 +35,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 62, + .rise_time_ns = 3, .fall_time_ns = 2, }"
# Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 170, - .fall_time_ns = 91, + .rise_time_ns = 3, + .fall_time_ns = 2, }"
# Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, - .fall_time_ns = 50, + .rise_time_ns = 16, + .fall_time_ns = 8, }"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tuning I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@7 PS1, Line 7: Tuning Imperativeb mood: Tune
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: spec Which spec?
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: Need Could be removed.
Hello Justin TerAvest, Marco Chen, build bot (Jenkins), Martin Roth, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35298
to look at the new patch set (#2).
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock
Tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock frequency less than 400KHz
Signed-off-by: Peichao.Wang peichao.wang@bitland.corp-partner.google.com Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35298/2
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@7 PS1, Line 7: Tuning
Imperativeb mood: Tune
Done
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: Need
Could be removed.
Done
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: spec
Which spec?
I2C protocol requirement---CLK need less than 400KHz. I will update it to ticket. Wait for a moment.
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: Need
Done
Done
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: spec
I2C protocol requirement---CLK need less than 400KHz. I will update it to ticket. Wait for a moment.
Done
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 2: Code-Review+2
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35298/1//COMMIT_MSG@9 PS1, Line 9: spec
Done
Spec has been upload to issue ticket.
Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35298 )
Change subject: mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock ......................................................................
mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock
Tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock frequency less than 400KHz
Signed-off-by: Peichao.Wang peichao.wang@bitland.corp-partner.google.com Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298 Reviewed-by: Martin Roth martinroth@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Peichao Li: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index beb99e0..2e25340 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -35,22 +35,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 62, + .rise_time_ns = 3, .fall_time_ns = 2, }"
# Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 170, - .fall_time_ns = 91, + .rise_time_ns = 3, + .fall_time_ns = 2, }"
# Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, - .fall_time_ns = 50, + .rise_time_ns = 16, + .fall_time_ns = 8, }"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \