Change in coreboot[master]: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit

[Wayne3 Wang (Code Review)]

Attention is currently required from: Hank Lin, Tim Wawrzynczak, Nick Vaccaro, Ken Lu, Zhuohao Lee.
Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50103 )

Change subject: mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
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Patch Set 1:

(2 comments)

File src/mainboard/google/volteer/variants/drobit/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/50103/comment/4e494898_bff00bee 
PS1, Line 63: 		device ref tbt_pcie_rp0 on end
            : 		device ref tbt_pcie_rp1 on end
> Do you check the FW_CONFIG in the CBI? The bit 0-3 should be set to 0011b. […]

I rewrite the CBI value of the system from 814206 to 814203. The issue of system hangs cannot be duplicated. For this result, should i modify the config.star of drobit? But it seems to be not match with the hardware design.

https://review.coreboot.org/c/coreboot/+/50103/comment/36f25e71_d912d6ef 
PS1, Line 63: 		device ref tbt_pcie_rp0 on end
            : 		device ref tbt_pcie_rp1 on end
> Do you check the FW_CONFIG in the CBI? The bit 0-3 should be set to 0011b. […]

I rewrite the CBI value of the system from 814206 to 814203. The issue of system hangs cannot be duplicated. For this result, should i modify the config.star of drobit? But it seems to be not match with the hardware design.