Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage - coreboot-gerrit

5 Oct 2021


      Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 )
Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
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Patch Set 1:
(1 comment)
File src/soc/amd/common/block/psp/psp_efs.c:
https://review.coreboot.org/c/coreboot/+/58115/comment/d15719c4_27916827 
PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
What is the reasoning for changing this?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Gerrit-Change-Number: 58115
Gerrit-PatchSet: 1
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