Change in coreboot[master]: mb/51nb/x210/gpio: Remove comments that contain pad functions
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
mb/51nb/x210/gpio: Remove comments that contain pad functions
Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have.
Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45371/1
diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index ac93d08..c6997f2 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -22,170 +22,170 @@
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), -/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP), -/* GPIO */ PAD_NC(GPP_A8, 20K_PU), -/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK), -/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), -/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_A18, NONE), -/* GPIO */ PAD_NC(GPP_A19, NONE), -/* GPIO */ PAD_NC(GPP_A20, NONE), -/* GPIO */ PAD_NC(GPP_A21, NONE), -/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B2, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* GPIO */ PAD_NC(GPP_B15, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_B19, NONE), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), -/* RESERVED - GPP_C6 */ -/* RESERVED - GPP_C7 */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), -/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), -/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), -/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), -/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), -/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), -/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), -/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), -/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), -/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_E2, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_E4, NONE), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), -/* GPIO */ PAD_NC(GPP_E7, NONE), -/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_E12, NONE), -/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), -/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* GPIO */ PAD_NC(GPD7, NONE), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), -/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), -/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), -/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), -/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), -/* SATAXPCIE7 */ PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP3 */ PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP4 */ PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP5 */ PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP6 */ PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP7 */ PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), -/* n/a */ PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), -/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), -/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), -/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), -/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_NC(GPP_A8, 20K_PU), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A12, 0, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_NC(GPP_B15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), };
#endif
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG@9 PS1, Line 9: Remove these comments, because it does not contain useful information : that helps to understand the circuit, which we do not have. I'm confused, how does removing the comments make understanding the GPIO config more clear?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG@9 PS1, Line 9: Remove these comments, because it does not contain useful information : that helps to understand the circuit, which we do not have.
I'm confused, how does removing the comments make understanding the GPIO config more clear?
It doesn't; the point is, that without schematics we can't really make sense of gpio.h with or without comments. Thus, drop the comments, that don't help anyway.
This was done for x11-lga-series, and another one I don't remember, too.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 1: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45371/1//COMMIT_MSG@9 PS1, Line 9: Remove these comments, because it does not contain useful information : that helps to understand the circuit, which we do not have.
It doesn't; the point is, that without schematics we can't really make sense of gpio. […]
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45371/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45371/2//COMMIT_MSG@9 PS2, Line 9: it does they do
Hello build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45371
to look at the new patch set (#3).
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
mb/51nb/x210/gpio: Remove comments that contain pad functions
Remove these comments, because they do not contain useful information that helps to understand the circuit, which we do not have.
Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45371/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45371/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45371/2//COMMIT_MSG@9 PS2, Line 9: it does
they do
Done Thx
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45371 )
Change subject: mb/51nb/x210/gpio: Remove comments that contain pad functions ......................................................................
mb/51nb/x210/gpio: Remove comments that contain pad functions
Remove these comments, because they do not contain useful information that helps to understand the circuit, which we do not have.
Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45371 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index f6d6519..34ee409 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -22,170 +22,170 @@
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), -/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP), -/* GPIO */ PAD_NC(GPP_A8, 20K_PU), -/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK), -/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), -/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_A18, NONE), -/* GPIO */ PAD_NC(GPP_A19, NONE), -/* GPIO */ PAD_NC(GPP_A20, NONE), -/* GPIO */ PAD_NC(GPP_A21, NONE), -/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B2, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* GPIO */ PAD_NC(GPP_B15, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_B19, NONE), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), -/* RESERVED - GPP_C6 */ -/* RESERVED - GPP_C7 */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), -/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), -/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), -/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), -/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), -/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), -/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), -/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), -/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), -/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_E2, NONE), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_NC(GPP_E4, NONE), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), -/* GPIO */ PAD_NC(GPP_E7, NONE), -/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_E12, NONE), -/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), -/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), -/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* GPIO */ PAD_NC(GPD7, NONE), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), -/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), -/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), -/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), -/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), -/* SATAXPCIE7 */ PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP3 */ PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP4 */ PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP5 */ PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP6 */ PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), -/* SATA_DEVSLP7 */ PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), -/* n/a */ PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), -/* n/a */ PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), -/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), -/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), -/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), -/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_NC(GPP_A8, 20K_PU), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A12, 0, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_NC(GPP_B15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), };
#endif
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Maxim Polyakov (Code Review)
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Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)