Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree

[Werner Zeh (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58740

to look at the new patch set (#3).

Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
......................................................................

mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree

On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58740/3