Change in coreboot[master]: mb/intel/adlrvp_m: add ec device entry to devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54490 )

Change subject: mb/intel/adlrvp_m: add ec device entry to devicetree
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mb/intel/adlrvp_m: add ec device entry to devicetree

TEST=Boot to OS and verify acpi tables.

Signed-off-by: Bora Guvendik 
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: John Zhao 
Reviewed-by: John Zhao 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  John Zhao: Looks good to me, approved
  John Zhao: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
index 80450e7..68a1bfa 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
@@ -1,5 +1,12 @@
 chip soc/intel/alderlake
    device domain 0 on
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				device pnp 0c09.0 on end
+			end
+		end # eSPI
    	device pci 1f.2 hidden

# The pmc_mux chip driver is a placeholder for the