Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33041
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
mb/lenovo/x60: Override default SPI OPs
The thinkpad X60 with SST flash needs different SPI OPs to make flashrom happy. flashrom uses AAI for writing.
One potential issue is that fast_read is not possible anymore, but on x86 the flash is memory mapped so this won't matter.
Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33041/1
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 274a151..3aef020 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */
+#include <spi_flash.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/device.h> @@ -26,6 +27,7 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h>
#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
@@ -66,6 +68,28 @@ return ARRAY_SIZE(cst_entries); }
+ +static const struct intel_spi_config spi_config_sst = { + .opprefixes = {0x06, 0x50}, + .ops = {{0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ + {0x04, WRITE_NO_ADDR}} /* Write Disable */ +}; + +void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + + if (strcmp(flash->name, "SST25VF016B") == 0) { + memcpy(spi_config, &spi_config_sst, sizeof(spi_config_sst)); + } +} + static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev;
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33041/1/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/1/src/mainboard/lenovo/x60/mainboard.c... PS1, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33041/2/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/2/src/mainboard/lenovo/x60/mainboard.c... PS2, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/33041/3/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/3/src/mainboard/lenovo/x60/mainboard.c... PS3, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
Hello Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33041
to look at the new patch set (#4).
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
mb/lenovo/x60: Override default SPI OPs
The thinkpad X60 with SST flash needs different SPI OPs to make flashrom happy. flashrom uses AAI for writing.
One potential issue is that fast_read is not possible anymore, but on x86 the flash is memory mapped so this won't matter.
Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33041/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33041/4/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/4/src/mainboard/lenovo/x60/mainboard.c... PS4, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/33041/5/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/5/src/mainboard/lenovo/x60/mainboard.c... PS5, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/33041/5/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/5/src/mainboard/lenovo/x60/mainboard.c... PS5, Line 89: memcpy(spi_config, &spi_config_sst, sizeof(spi_config_sst)); Struct of same type can be assigned, IIRC:
*spi_config = spi_config_sst;
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/33041/6/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/6/src/mainboard/lenovo/x60/mainboard.c... PS6, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/33041/7/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/7/src/mainboard/lenovo/x60/mainboard.c... PS7, Line 81: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/33041/8/src/mainboard/lenovo/x60/mainboard.c File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/#/c/33041/8/src/mainboard/lenovo/x60/mainboard.c... PS8, Line 82: {0x04, WRITE_NO_ADDR}} /* Write Disable */ space required after that close brace '}'
Hello Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33041
to look at the new patch set (#9).
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
mb/lenovo/x60: Override default SPI OPs
The thinkpad X60 with SST flash needs different SPI OPs to make flashrom happy. flashrom uses AAI for writing.
One potential issue is that fast_read is not possible anymore, but on x86 the flash is memory mapped so this won't matter.
Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33041/9
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
Patch Set 12: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/33041/12/src/mainboard/lenovo/x60/m... File src/mainboard/lenovo/x60/mainboard.c:
https://review.coreboot.org/c/coreboot/+/33041/12/src/mainboard/lenovo/x60/m... PS12, Line 75: .ops = {{0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ Put a line break between the opening braces?
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
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Arthur Heymans has restored this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
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Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33041 )
Change subject: mb/lenovo/x60: Override default SPI OPs ......................................................................
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