Attention is currently required from: Arthur Heymans, Martin L Roth, Nick Vaccaro.
Alicja Michalska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email )
Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi, It looks like you haven't contributed to the coreboot project before. […]
Hello Martin! Thank you for warm welcome ❤️
It's my first time submitting patches via gerrit. So far, I've only been submitting them to/telling MrChromebox (Matt) what to change, and those patches eventually made it to upstream in one form or another.
I'm *mostly* familiar with coding style, as it's very similar to Linux (and I do contribute to the Linux kernel). I'll read the guidelines you've linked to though.
You can find me on OSFW Slack under my usual handle, '@elly' if you need more information.
As for merging those patches, I've tested them with TGL-H (port I just submitted), as well as TGL-UP (Google/Volteer/ELDRID, which doesn't have PCIE4.0) for sanity check and I don't see any regressions whatsoever.
Currently have the system running with patch applied - Coreboot 24.02, Linux 6.7.7, and 4 days of uptime. PEG0 == 06.0: +-06.0-[04]----00.0 Kingston Technology Company, Inc. KC3000/FURY Renegade NVMe SSD E18 [2646:5013] Subsystem: Kingston Technology Company, Inc. KC3000/FURY Renegade NVMe SSD E18 [2646:5013] Interrupt: pin A routed to IRQ 16
Previous patch in this series is required for Coreboot to recognize the CPU family - otherwise booting the platform with pre-production stepping (TGL-H D0) results in [EMERG] Unknown CPU. Of course Intel doesn't carry microcode for that stepping in their tree, but it can be found publicly. I spoke to Felix during FOSDEM and he assured me merging this shouldn't be a problem since it's just a CPUID definition 😊
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Alicja Michalska (Code Review)