Change in coreboot[master]: mb/google/soraka: Camera PMIC runtime power control

[Naresh Solanki (Code Review)]

Hello Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/20741

to review the following change.

Change subject: mb/google/soraka: Camera PMIC runtime power control
......................................................................

mb/google/soraka: Camera PMIC runtime power control

Currently PMIC(tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.

With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow runtime power saving when
camera is not in use.

PMIC will be reset in first boot & not in S3 & S0ix resume.

Also remove the smihandler for PMIC power management & handle it as part
of sensor and VCM ACPI PowerResource.

BUG=b:63903239
TEST= Build for Saraka. Check Camera probe, Capture image before & after
S3 & S0ix resume.

Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi 
Signed-off-by: Naresh G Solanki 
---
M src/mainboard/google/poppy/acpi/mipi_camera.asl
M src/mainboard/google/poppy/smihandler.c
M src/mainboard/google/poppy/variants/soraka/gpio.c
3 files changed, 52 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/20741/8

diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl
index 5c75122..68122a6 100644
--- a/src/mainboard/google/poppy/acpi/mipi_camera.asl
+++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl
@@ -27,6 +27,55 @@
    		Return (0x0F)
    	}

+		Method (PMON, 0, Serialized) {
+			/*
+			 * Turn on 3V3_VDD. It takes around 1 ms
+			 * for volatge to settle to 3.3 Volt.
+			 * Provide additional 2 ms before we
+			 * enable regulators.
+			 */
+			STXS(EN_PP3300_DX_CAM)
+			Sleep (3)
+		}
+
+		Method (PMOF, 0, Serialized) {
+			/*
+			 * Make Sure all PMIC outputs are off.
+			 */
+			If (LEqual (VSIC, Zero)) {
+				CTXS(EN_PP3300_DX_CAM)
+			}
+		}
+
+		Name (_PR0, Package (0x01) { CPMC })
+		Name (_PR3, Package (0x01) { CPMC })
+
+		/* Power resource methods for PMIC */
+		PowerResource (CPMC, 0, 0) {
+			Name (RSTO, 1)
+			Method (_ON, 0, Serialized) {
+			/*
+			 * Reset PMIC once during first boot.
+			 * This reset is avoided in S3 & S0ix resume.
+			 */
+			if (Lequal (RSTO, 1))
+			{
+				CTXS(EN_CAM_PMIC_RST_L)
+				Sleep(1)
+				STXS(EN_CAM_PMIC_RST_L)
+				RSTO = 0
+			}
+			PMON()
+			}
+			Method (_OFF, 0, Serialized) {
+				PMOF()
+			}
+			Method (_STA, 0, Serialized) {
+				Local0 = GTXS(EN_PP3300_DX_CAM)
+				Return (Local0)
+			}
+		}
+
    	/* Marks the availability of all the operation regions */
    	Name (AVBL, Zero)
    	Name (AVGP, Zero)
@@ -289,6 +338,7 @@
    					Decrement (VSIC)
    					If (LEqual (VSIC, Zero)) {
    						VSIO = 0
+							PMOF()
    					}
    				}
    			} ElseIf (LEqual (Arg0, 1)) {
@@ -296,6 +346,7 @@
    				If (LLess (VSIC, 3)) {
    					/* Turn on VSIO */
    					If (LEqual (VSIC, Zero)) {
+							PMON()
    						VSIO = 3
    					}
    					Increment (VSIC)
diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c
index 1a86d0f..70d0ab4 100644
--- a/src/mainboard/google/poppy/smihandler.c
+++ b/src/mainboard/google/poppy/smihandler.c
@@ -27,17 +27,10 @@
    chromeec_smi_process_events();
 }

-static void mainboard_gpio_smi_sleep(void)
-{
-	/* Power down camera PMIC */
-	gpio_set(EN_PP3300_DX_CAM, 0);
-}
-
 void mainboard_smi_sleep(u8 slp_typ)
 {
    chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
    		MAINBOARD_EC_S5_WAKE_EVENTS);
-	mainboard_gpio_smi_sleep();
 }

int mainboard_smi_apmc(u8 apmc)
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index 6e0a54f..bf11894 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -143,7 +143,7 @@
    /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
    PAD_CFG_GPO(GPP_C10, 1, DEEP),
    /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
-	PAD_CFG_GPO(GPP_C11, 1, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
    /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
    PAD_CFG_GPI(GPP_C12, NONE, DEEP),
    /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */