Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25921
Change subject: Documentation/Intel: Add MultiProcessorInit documentation ......................................................................
Documentation/Intel: Add MultiProcessorInit documentation
Add documentation for MP service PPI using EFI interface on Intel 9th Gen Platforms.
Documented so far: * Problem Statement * New Design Proposal * API interface * Code Flow changes * Benefits
BRANCH=none BUG=b:74436746 TEST=none
Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Signed-off-by: Subrata Banik subrata.banik@intel.com --- A Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png A Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md 2 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/25921/1
diff --git a/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png new file mode 100644 index 0000000..5836140 --- /dev/null +++ b/Documentation/Intel/MultiProcessorInit/Coreboot_Publish_MP_Service_API.png Binary files differ diff --git a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md new file mode 100644 index 0000000..6187631 --- /dev/null +++ b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md @@ -0,0 +1,74 @@ +# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI + +## Introduction + +This documentation is intended to document the purpose for creating EFI service +Interface inside Coreboot space to perform CPU feature programming on Application +Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs. + +Today Coreboot is capable enough to handle multi-processor initialization on IA platforms. + +The multi-processor initialization code has to take care of lots of duties: + +1 Bringing all cores out of reset +2 Load latest microcode on all cores +3 Sync latest MTRR snapshot between BSP and APs +4 Perform sets of CPU feature programming + * CPU Power & Thermal Management + * Overclocking + * Intel Trusted Execution Technology + * Intel Software Guard Extensions + * Intel Processor Trace etc. + +This above CPU feature programming lists are expected to grow with current and future +CPU complexity and there might be some cases where certain feature programming mightbe +closed source in nature. + +Platform code might need to compromise on those closed source nature of CPU programming +if we don't plan to provide an alternate interface which can be used by Coreboot to +get-rid of such close source CPU programming. + +## Proposal + +As Coreboot is doing CPU multi-processor initialization for IA platform before FSP-S +initialization and having all possible information about cores in terms of maximum number +of cores, APIC ids, stack size etc. It’s also possible for Coreboot to extend its own +support model and create a sets of APIs which later can be used by FSP to run CPU feature +programming using Coreboot published APIs. + +Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate +PPI to perform certain API call, hence Coreboot has to created MP services APIs known as +EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9. +More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf + +### Coreboot to publish EFI_MP_SERVICES_PPI APIs +| API | Description | +|------------------------------|------------------------------------------------------------------| +| PeiGetNumberOfProcessors | Get the number of CPU's. | +| PeiGetProcessorInfo | Get information on a specific CPU. | +| PeiStartupAllAPs | Activate all of the application processors. | +| PeiStartupThisAP | Activate a specific application processor. | +| PeiSwitchBSP | Switch the boot strap processor. | +| PeiEnableDisableAP | Enable or disable an application processor. | +| PeiWhoAmI | Identify the currently executing processor. | +|------------------------------|------------------------------------------------------------------| + + +## Code Flow + +Here is proposed design flow with Coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make +use of the same to perform some CPU feature programming. + +** Coreboot-FSP MP init flow ** +![alt text][Coreboot_Publish_MP_Service_API] + +[Coreboot_Publish_MP_Service_API]: Coreboot_Publish_MP_Service_API.png "Coreboot-FSP MP init flow" + +## Benefits +1. Coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming. +With proposed model, Coreboot will make use of SkipMpInit=0 which will allow to run all +Silicon recommended CPU programming. +2. CPU feature programming inside FSP will be more transparent than before as it’s using +Coreboot interfaces to execute those programming. +3. Coreboot will have more control over running those feature programming as API optimization +handled by Coreboot.
-
Subrata Banik (Code Review)