Change in coreboot[master]: soc/intel/skylake: Use set_dev_state_by_devicetree()

[Felix Singer (Code Review)]

Attention is currently required from: Patrick Rudolph.
 Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52810 )

Change subject: soc/intel/skylake: Use set_dev_state_by_devicetree()
......................................................................

soc/intel/skylake: Use set_dev_state_by_devicetree()

Change-Id: I75088098a4cceea2e860ca97c4853d2e5279c2f2
Signed-off-by: Felix Singer 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/romstage/fsp_params.c
2 files changed, 36 insertions(+), 63 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/52810/1

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d4d8938..8830697 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -5,6 +5,7 @@
 #include <fsp/api.h>
 #include <acpi/acpi.h>
 #include <console/console.h>
+#include <device/devenmap.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include <fsp/util.h>
@@ -234,6 +235,25 @@

mainboard_silicon_init_params(params);

+	const struct device_enable_map devmap[] = {
+		{ &params->Device4Enable,		SA_DEVFN_TS },
+		{ &params->GmmEnable,			SA_DEVFN_GMM },
+		{ &params->SaImguEnable,		SA_DEVFN_IMGU },
+		{ &tconfig->ChapDeviceEnable,		SA_DEVFN_CHAP },
+		{ &params->PchCio2Enable,		PCH_DEVFN_CIO },
+		{ &params->PchLanEnable,		PCH_DEVFN_GBE },
+		{ &params->PchIshEnable,		PCH_DEVFN_ISH },
+		{ &params->PchHdaEnable,		PCH_DEVFN_HDA },
+		{ &params->ShowSpiController,		PCH_DEVFN_SPI },
+		{ &params->ScsEmmcEnabled,		PCH_DEVFN_EMMC },
+		{ &params->SataEnable,			PCH_DEVFN_SATA },
+		{ &params->XdciEnable,			PCH_DEVFN_USBOTG },
+		{ &params->ScsSdCardEnabled,		PCH_DEVFN_SDCARD },
+		{ &params->PchThermalDeviceEnable,	PCH_DEVFN_THERMAL },
+	};
+
+	set_dev_state_by_devicetree(devmap, ARRAY_SIZE(devmap));
+
    struct soc_power_limits_config *soc_confg;
    config_t *confg = config_of_soc();
    soc_confg = &confg->power_limits_config;
@@ -283,8 +303,6 @@
    	}
    }

-	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
-	params->SataEnable = dev && dev->enabled;
    if (params->SataEnable) {
    	memcpy(params->SataPortsEnable, config->SataPortsEnable,
    			sizeof(params->SataPortsEnable));
@@ -350,15 +368,6 @@
    memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
           sizeof(params->SerialIoDevMode));

-	dev = pcidev_path_on_root(PCH_DEVFN_CIO);
-	params->PchCio2Enable = dev && dev->enabled;
-
-	dev = pcidev_path_on_root(SA_DEVFN_IMGU);
-	params->SaImguEnable = dev && dev->enabled;
-
-	dev = pcidev_path_on_root(SA_DEVFN_CHAP);
-	tconfig->ChapDeviceEnable = dev && dev->enabled;
-
    dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
    params->Heci3Enabled = dev && dev->enabled;

@@ -368,8 +377,6 @@
    params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable;
    params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;

-	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
-	params->PchLanEnable = dev && dev->enabled;
    if (params->PchLanEnable) {
    	params->PchLanLtrEnable = config->EnableLanLtr;
    	params->PchLanK1OffEnable = config->EnableLanK1Off;
@@ -378,13 +385,8 @@
    }
    params->SsicPortEnable = config->SsicPortEnable;

-	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
-	params->ScsEmmcEnabled = dev && dev->enabled;
    params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;

-	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
-	params->ScsSdCardEnabled = dev && dev->enabled;
-
    if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
    	params->PchScsEmmcHs400DllDataValid =
    		!!config->EmmcHs400DllNeed;
@@ -394,22 +396,10 @@
    		config->ScsEmmcHs400TxDataDll;
    }

-	/* If ISH is enabled, enable ISH elements */
-	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
-	params->PchIshEnable = dev && dev->enabled;
-
-	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
-	params->PchHdaEnable = dev && dev->enabled;
-
    params->PchHdaVcType = config->PchHdaVcType;
    params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
    params->PchHdaDspEnable = config->DspEnable;

-	dev = pcidev_path_on_root(SA_DEVFN_TS);
-	params->Device4Enable = dev && dev->enabled;
-	dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
-	params->PchThermalDeviceEnable = dev && dev->enabled;
-
    tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
    tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
    tconfig->PowerLimit4 = 0;
@@ -466,23 +456,10 @@
    for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
    	fill_vr_domain_config(params, i, &config->domain_vr_config[i]);

-	/* Show SPI controller if enabled in devicetree.cb */
-	dev = pcidev_path_on_root(PCH_DEVFN_SPI);
-	params->ShowSpiController = dev && dev->enabled;

-	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
-	if (dev) {
-		if (!xdci_can_enable())
-			dev->enabled = 0;
-		params->XdciEnable = dev->enabled;
-	} else {
+	/* Disable xDCI controller if not allowed */
+	if (!xdci_can_enable())
    	params->XdciEnable = 0;
-	}
-
-	/* Enable or disable Gaussian Mixture Model in devicetree */
-	dev = pcidev_path_on_root(SA_DEVFN_GMM);
-	params->GmmEnable = dev && dev->enabled;

/*
     * Send VR specific mailbox commands:
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c
index 294bf44..be61d87 100644
--- a/src/soc/intel/skylake/romstage/fsp_params.c
+++ b/src/soc/intel/skylake/romstage/fsp_params.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <device/devenmap.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <soc/iomap.h>
@@ -11,6 +12,7 @@
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>

+
 static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
 {
    msr_t flex_ratio;
@@ -27,7 +29,6 @@
    		FSP_M_TEST_CONFIG *m_t_cfg,
    		const struct soc_intel_skylake_config *config)
 {
-	const struct device *dev;
    /*
     * To enable or disable the corresponding PEG root port you need to
     * add to the devicetree.cb:
@@ -38,8 +39,6 @@
     * If PEG port is not defined in the device tree, it will be disabled
     * in FSP
     */
-	dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
-	m_cfg->Peg0Enable = dev && dev->enabled;
    if (m_cfg->Peg0Enable) {
    	m_cfg->Peg0Enable = 2;
    	m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
@@ -52,8 +51,6 @@
    	m_t_cfg->Peg0Gen3EqPh3Method = 0;
    }

-	dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
-	m_cfg->Peg1Enable = dev && dev->enabled;
    if (m_cfg->Peg1Enable) {
    	m_cfg->Peg1Enable = 2;
    	m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
@@ -63,8 +60,6 @@
    	m_t_cfg->Peg1Gen3EqPh3Method = 0;
    }

-	dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
-	m_cfg->Peg2Enable = dev && dev->enabled;
    if (m_cfg->Peg2Enable) {
    	m_cfg->Peg2Enable = 2;
    	m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
@@ -109,10 +104,7 @@
 static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
    			const struct soc_intel_skylake_config *config)
 {
-	const struct device *dev;
-
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
+	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && m_cfg->InternalGfx;

/*
     * If iGPU is enabled, set IGD stolen size to 64MB. The FBC
@@ -132,12 +124,22 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    const struct soc_intel_skylake_config *config;
-	const struct device *dev;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;

config = config_of_soc();

+	const struct device_enable_map devmap[] = {
+		{ &m_cfg->InternalGfx,	SA_DEVFN_IGD },
+		{ &m_cfg->Peg0Enable,	SA_DEVFN_PEG0 },
+		{ &m_cfg->Peg1Enable,	SA_DEVFN_PEG1 },
+		{ &m_cfg->Peg2Enable,	SA_DEVFN_PEG2 },
+		{ &m_cfg->SmbusEnable,	PCH_DEVFN_SMBUS },
+		{ &m_cfg->EnableTraceHub, PCH_DEVFN_TRACEHUB },
+	};
+
+	set_dev_state_by_devicetree(devmap, ARRAY_SIZE(devmap));
+
    soc_memory_init_params(m_cfg, config);
    soc_peg_init_params(m_cfg, m_t_cfg, config);

@@ -154,15 +156,9 @@
    /* DCI and TraceHub configs */
    m_t_cfg->PchDciEn = config->PchDciEn;

-	dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
-	m_cfg->EnableTraceHub = dev && dev->enabled;
    m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
    m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;

-	/* Enable SMBus controller */
-	dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
-	m_cfg->SmbusEnable = dev && dev->enabled;
-
    /* Set primary graphic device */
    soc_primary_gfx_config_params(m_cfg, config);
    m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;