Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81586?usp=email )
Change subject: util/intelp2m: Add support for TigerLake-H SoC ......................................................................
util/intelp2m: Add support for TigerLake-H SoC
Add support for TigerLake Halo SoC, based on CNL profile.
Test: Convert GPIO dump from inteltool into coreboot macros for out-of-tree TGL board.
Change-Id: I26eff225c2045edfe5836283be7b4c63f6b405e8 Signed-off-by: Alicja Michalska ahplka19@gmail.com --- M util/intelp2m/config/config.go A util/intelp2m/generate/gpio.h A util/intelp2m/intelp2m M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/tgl/macro.go A util/intelp2m/platforms/tgl/template.go 7 files changed, 572 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81586/1
diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go index 7b491b1..62242b9 100644 --- a/util/intelp2m/config/config.go +++ b/util/intelp2m/config/config.go @@ -28,8 +28,9 @@ LewisburgType uint8 = 1 ApolloType uint8 = 2 CannonType uint8 = 3 - AlderType uint8 = 4 - JasperType uint8 = 5 + TigerType uint8 = 4 + AlderType uint8 = 5 + JasperType uint8 = 6 )
var key uint8 = SunriseType @@ -39,6 +40,7 @@ "lbg": LewisburgType, "apl": ApolloType, "cnl": CannonType, + "tgl": TigerType, "adl": AlderType, "jsl": JasperType, } @@ -67,6 +69,9 @@ func IsPlatformCannonLake() bool { return IsPlatform(CannonType) } +func IsPlatformTigerLake() bool { + return IsPlatform(TigerType) +} func IsPlatformAlderLakeH() bool { return IsPlatform(AlderType) } diff --git a/util/intelp2m/generate/gpio.h b/util/intelp2m/generate/gpio.h new file mode 100644 index 0000000..52a6975 --- /dev/null +++ b/util/intelp2m/generate/gpio.h @@ -0,0 +1,423 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_GPO(GPP_R0, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_R1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_CFG_GPO(GPP_R2, 0, PLTRST), + PAD_CFG_GPO(GPP_R3, 1, PLTRST), + PAD_CFG_GPO(GPP_R4, 0, PLTRST), + PAD_NC(GPP_R5, NONE), + _PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_R10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_R11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + PAD_NC(GPP_R16, NONE), + PAD_NC(GPP_R17, NONE), + PAD_CFG_GPO(GPP_R18, 1, PLTRST), + PAD_NC(GPP_R19, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 1, PLTRST), + PAD_NC(GPP_B1, NONE), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, PLTRST), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_B13, NONE), + PAD_NC(GPP_B14, NONE), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + + /* ------- GPIO Group VGPIO0 ------- */ + PAD_CFG_GPO(VGPIO_USB_0, 1, PLTRST), + _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(VGPIO_USB_9, 1, DEEP), + _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_D11, 1, PLTRST), + PAD_CFG_GPO(GPP_D12, 1, PLTRST), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPO(GPP_C5, 0, DEEP), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), + PAD_CFG_GPO(GPP_C14, 1, PLTRST), + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_S ------- */ + _PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPO(GPP_G1, 0, DEEP), + PAD_CFG_GPO(GPP_G2, 0, PLTRST), + PAD_CFG_GPO(GPP_G3, 1, PLTRST), + PAD_CFG_GPO(GPP_G4, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_CFG_GPO(GPP_G6, 1, PLTRST), + PAD_CFG_GPO(GPP_G7, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + + /* ------- GPIO Group VGPIO ------- */ + _PAD_CFG_STRUCT(VGPIO0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_CFG_GPO(VGPIO4, 0, DEEP), + _PAD_CFG_STRUCT(VGPIO5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(VGPIO6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(VGPIO7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + PAD_CFG_NF(VGPIO8, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO9, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(VGPIO10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + _PAD_CFG_STRUCT(VGPIO11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + PAD_CFG_NF(VGPIO12, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO13, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(VGPIO18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + _PAD_CFG_STRUCT(VGPIO19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + PAD_CFG_NF(VGPIO20, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO21, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(VGPIO22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + _PAD_CFG_STRUCT(VGPIO23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + PAD_CFG_NF(VGPIO24, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO25, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(VGPIO30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + PAD_CFG_NF(VGPIO31, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO32, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO33, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO34, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO35, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO36, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPD7, 0, PWROK), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_E ------- */ + _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_E2, 1, PLTRST), + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_CFG_GPO(GPP_E6, 1, PLTRST), + PAD_NC(GPP_E7, NONE), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPO(GPP_F3, 0, PLTRST), + PAD_CFG_GPO(GPP_F4, 1, PLTRST), + PAD_CFG_GPO(GPP_F5, 1, PLTRST), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + PAD_NC(GPP_F10, NONE), + PAD_CFG_GPO(GPP_F11, 1, PLTRST), + PAD_CFG_GPO(GPP_F12, 1, DEEP), + PAD_CFG_GPO(GPP_F13, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_F16, 1, PLTRST), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + + /* ------- GPIO Group VGPIO3 ------- */ + PAD_CFG_NF(VGPIO_PCIE_0, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_1, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_2, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_3, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_4, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_5, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_6, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_7, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_8, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_9, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_10, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_11, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_12, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_13, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_14, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_15, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_16, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_17, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_18, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_19, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_20, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_21, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_22, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_23, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_24, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_25, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_26, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_27, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_28, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_29, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_30, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_31, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_32, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_33, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_34, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_35, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_36, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_37, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_38, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_39, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_40, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_41, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_42, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_43, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_44, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_45, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_46, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_47, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_64, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_65, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_66, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_67, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_68, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_69, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_70, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_71, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_72, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_73, NONE, PLTRST, NF1), + _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0), + PAD_CFG_NF(VGPIO_PCIE_75, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_77, NONE, PLTRST, NF1), + _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | (1 << 1), 0), + PAD_CFG_NF(VGPIO_PCIE_79, NONE, PLTRST, NF1), + PAD_CFG_NF(VGPIO_PCIE_80, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO_PCIE_81, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO_PCIE_82, NONE, DEEP, NF1), + PAD_CFG_NF(VGPIO_PCIE_83, NONE, DEEP, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_NC(GPP_H11, NONE), + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_CFG_GPO(GPP_H16, 1, PLTRST), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPO(GPP_H18, 0, PLTRST), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPO(GPP_J0, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + PAD_NC(GPP_J6, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPO(GPP_J8, 1, PLTRST), + PAD_CFG_GPO(GPP_J9, 1, PLTRST), + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPO(GPP_K0, 1, PLTRST), + PAD_CFG_GPO(GPP_K1, 1, PLTRST), + PAD_CFG_GPO(GPP_K2, 1, PLTRST), + PAD_CFG_GPO(GPP_K3, 1, PLTRST), + PAD_CFG_GPO(GPP_K4, 1, PLTRST), + PAD_CFG_GPO(GPP_K5, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_CFG_GPO(GPP_K10, 1, PLTRST), + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + PAD_NC(GPP_I7, NONE), + PAD_CFG_GPO(GPP_I8, 1, PLTRST), + PAD_CFG_GPO(GPP_I9, 1, PLTRST), + PAD_CFG_GPO(GPP_I10, 1, PLTRST), + PAD_NC(GPP_I11, NONE), + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Group CPU ------- */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/util/intelp2m/intelp2m b/util/intelp2m/intelp2m new file mode 100755 index 0000000..7e337df --- /dev/null +++ b/util/intelp2m/intelp2m Binary files differ diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index b3835ff..64db9fee 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -70,6 +70,7 @@ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n"+ + "\ttgl - TigerLake-H SoC\n"+ "\tadl - AlderLake PCH\n"+ "\tjsl - Jasper Lake SoC\n")
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index 0e2a64b..a6fa315 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -11,6 +11,7 @@ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" "review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl" "review.coreboot.org/coreboot.git/util/intelp2m/config" @@ -150,6 +151,7 @@ config.CannonType : cnl.PlatformSpecific{ InheritanceTemplate : snr.PlatformSpecific{}, }, + config.TigerType : tgl.PlatformSpecific{}, config.AlderType : adl.PlatformSpecific{}, config.JasperType : jsl.PlatformSpecific{}, } diff --git a/util/intelp2m/platforms/tgl/macro.go b/util/intelp2m/platforms/tgl/macro.go new file mode 100644 index 0000000..3b436ee --- /dev/null +++ b/util/intelp2m/platforms/tgl/macro.go @@ -0,0 +1,115 @@ +package tgl + +import ( + "strings" + "fmt" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/config" + "review.coreboot.org/coreboot.git/util/intelp2m/fields" +) + +const ( + PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc + PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff +) + +const ( + PAD_CFG_DW0 = common.PAD_CFG_DW0 + PAD_CFG_DW1 = common.PAD_CFG_DW1 + MAX_DW_NUM = common.MAX_DW_NUM +) + +type InheritanceMacro interface { + Pull() + GpiMacroAdd() + GpoMacroAdd() + NativeFunctionMacroAdd() + NoConnMacroAdd() +} + +type PlatformSpecific struct { + InheritanceMacro +} + +// RemmapRstSrc - remmap Pad Reset Source Config +func (PlatformSpecific) RemmapRstSrc() { + macro := common.GetMacro() + if config.TemplateGet() != config.TempInteltool { + // Use reset source remapping only if the input file is inteltool.log dump + return + } + if strings.Contains(macro.PadIdGet(), "GPD") { + // See reset map for the TigerLake Community 2: + // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/gpi... + // remmap is not required because it is the same as common. + return + } + + dw0 := macro.Register(PAD_CFG_DW0) + var remapping = map[uint8]uint32{ + 0: common.RST_RSMRST << common.PadRstCfgShift, + 1: common.RST_DEEP << common.PadRstCfgShift, + 2: common.RST_PLTRST << common.PadRstCfgShift, + } + resetsrc, valid := remapping[dw0.GetResetConfig()] + if valid { + // dw0.SetResetConfig(resetsrc) + ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()] + dw0.ValueSet(ResetConfigFieldVal) + } else { + fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet()) + } + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) +} + +// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro +// as a new argument +func (platform PlatformSpecific) Pull() { + platform.InheritanceMacro.Pull() +} + +// Adds PAD_CFG_GPI macro with arguments +func (platform PlatformSpecific) GpiMacroAdd() { + platform.InheritanceMacro.GpiMacroAdd() +} + +// Adds PAD_CFG_GPO macro with arguments +func (platform PlatformSpecific) GpoMacroAdd() { + platform.InheritanceMacro.GpoMacroAdd() +} + +// Adds PAD_CFG_NF macro with arguments +func (platform PlatformSpecific) NativeFunctionMacroAdd() { + platform.InheritanceMacro.NativeFunctionMacroAdd() +} + +// Adds PAD_NC macro +func (platform PlatformSpecific) NoConnMacroAdd() { + platform.InheritanceMacro.NoConnMacroAdd() +} + +// GenMacro - generate pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string { + macro := common.GetInstanceMacro( + PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + }, + fields.InterfaceGet(), + ) + macro.Clear() + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields) + macro.PadIdSet(id).SetPadOwnership(ownership) + macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS) + macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS) + return macro.Generate() +} diff --git a/util/intelp2m/platforms/tgl/template.go b/util/intelp2m/platforms/tgl/template.go new file mode 100644 index 0000000..f98272a --- /dev/null +++ b/util/intelp2m/platforms/tgl/template.go @@ -0,0 +1,24 @@ +package tgl + +import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + +// GroupNameExtract - This function extracts the group ID, if it exists in a row +// line : string from the configuration file +// return +// bool : true if the string contains a group identifier +// string : group identifier +func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { + return common.KeywordsCheck(line, + "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", + "GPD", "GPP_E", "GPP_F", "GPP_H", "GPP_J", "GPP_K", "GPP_I", + "VGPIO_USB", "VGPIO_PCIE") + +} + +// KeywordCheck - This function is used to filter parsed lines of the configuration file and +// returns true if the keyword is contained in the line. +// line : string from the configuration file +func (PlatformSpecific) KeywordCheck(line string) bool { + isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO") + return isIncluded +}
-
Alicja Michalska (Code Review)