Change in coreboot[master]: Revert "soc/intel/skylake: storage: Add 2ms delay before exi...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20462

Change subject: Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"
......................................................................

Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"

Don't need this additional 2ms delay as PCR read after sideband write
help to fix original hard hang issue.

This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e.

Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/acpi/scs.asl
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/20462/1

diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl
index 60c546b..235a57e 100644
--- a/src/soc/intel/skylake/acpi/scs.asl
+++ b/src/soc/intel/skylake/acpi/scs.asl
@@ -86,7 +86,6 @@

/* Set bits 31, 6, 2, 0 */
    	^^PCRO (PID_SCS, 0x600, 0x80000045)
-		Sleep (2)

/* Set Power State to D0 */
    	And (PMCR, 0xFFFC, PMCR)
@@ -140,7 +139,6 @@

/* Set bits 8, 7, 2, 0 */
    	^^PCRO (PID_SCS, 0x600, 0x00000185)
-		Sleep (2)

/* Set Power State to D0 */
    	And (PMCR, 0xFFFC, PMCR)