Change in coreboot[master]: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40037 )

Change subject: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake
......................................................................

soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake

Current pin-ctrl kernel(v5.4) driver expects the firmware to publish
single GPIO ACPI device. Until kernel pin-ctrl driver implementation is
updated to consume community based GPIO ACPI device, updating the current
ACPI code to comply with pin-ctrl driver requirement.

BUG=b:150154277
TEST=Verify intel pin-ctrl driver can successfully load in OS

Change-Id: I5c88eb4f03fd59074c0bef336f389d6c0de97304
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/jasperlake/acpi/gpio.asl
1 file changed, 36 insertions(+), 73 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/40037/1

diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl
index 9bf0c60..47a1dac 100644
--- a/src/soc/intel/jasperlake/acpi/gpio.asl
+++ b/src/soc/intel/jasperlake/acpi/gpio.asl
@@ -11,108 +11,70 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
+#include <intelblocks/gpio.h>
 #include <soc/gpio_defs.h>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
-#include <intelblocks/gpio.h>
 #include "gpio_op.asl"

-Device (GCM0)
+Device (GPIO)
 {
    Name (_HID, CROS_GPIO_NAME)
    Name (_UID, 0)
-	Name (_DDN, "GPIO Controller Community 0")
+	Name (_DDN, "GPIO Controller")

Name (RBUF, ResourceTemplate()
    {
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM2)
+		Memory32Fixed (ReadWrite, 0, 0, COM4)
+		Memory32Fixed (ReadWrite, 0, 0, COM5)
    	Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
    		{ GPIO_IRQ14 }
    })
+
    Method (_CRS, 0, NotSerialized)
    {
+		/* GPIO Community 0 */
    	CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
-		BAS0 = ^^PCRB (PID_GPIOCOM0)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+		Store (^^PCRB (PID_GPIOCOM0), BAS0)
+		Store (GPIO_BASE_SIZE, LEN0)

-Device (GCM1)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 1)
-	Name (_DDN, "GPIO Controller Community 1")
-
-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-			{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 1 */
    	CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
-		BAS1 = ^^PCRB (PID_GPIOCOM1)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+		Store (^^PCRB (PID_GPIOCOM1), BAS1)
+		Store (GPIO_BASE_SIZE, LEN1)

-Device (GCM4)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 4)
-	Name (_DDN, "GPIO Controller Community 4")
+		/* GPIO Community 2 */
+		CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
+		CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
+		Store (^^PCRB (PID_GPIOCOM2), BAS2)
+		Store (GPIO_BASE_SIZE, LEN2)

-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-			{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 4 */
    	CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
-		BAS4 = ^^PCRB (PID_GPIOCOM4)
-		Return (^RBUF)
-	}
-	Method (_STA)
-	{
-		Return (0xF)
-	}
-}
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+		Store (^^PCRB (PID_GPIOCOM4), BAS4)
+		Store (GPIO_BASE_SIZE, LEN4)

-Device (GCM5)
-{
-	Name (_HID, CROS_GPIO_NAME)
-	Name (_UID, 5)
-	Name (_DDN, "GPIO Controller Community 5")
-
-	Name (RBUF, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
-		{ GPIO_IRQ14 }
-	})
-	Method (_CRS, 0, NotSerialized)
-	{
+		/* GPIO Community 5 */
    	CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
-		BAS5 = ^^PCRB (PID_GPIOCOM5)
-		Return (^RBUF)
+		CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+		Store (^^PCRB (PID_GPIOCOM5), BAS5)
+		Store (GPIO_BASE_SIZE, LEN5)
+
+		Return (RBUF)
    }
-	Method (_STA)
+
+	Method (_STA, 0, NotSerialized)
    {
    	Return (0xF)
    }
 }
-
 /*
  * Get GPIO DW0 Address
  * Arg0 - GPIO Number
@@ -153,3 +115,4 @@
    Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
    Return (Local2)
 }
+

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40037 )

Change subject: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG@9 
PS1, Line 9: kernel(v5.4)
kernel v5.4

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG@11 
PS1, Line 11: updating
update

[Aamir Bohra (Code Review)]

Aamir Bohra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40037 )

Change subject: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake
......................................................................

Abandoned

duplicate: https://review.coreboot.org/c/coreboot/+/39470

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40037 )

Change subject: soc/intel/jasperlake: Publish single GPIO ACPI device for Jasper Lake
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG@9 
PS1, Line 9: kernel(v5.4)
> kernel v5. […]

Updated https://review.coreboot.org/c/coreboot/+/39470 as per review comment

https://review.coreboot.org/c/coreboot/+/40037/1//COMMIT_MSG@11 
PS1, Line 11: updating
> update

Updated https://review.coreboot.org/c/coreboot/+/39470 as per review comment