Change in coreboot[master]: riscv: add support move bootblock to CAR/SRAM before exection

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27645

Change subject: riscv: add support move bootblock to CAR/SRAM before exection
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riscv: add support move bootblock to CAR/SRAM before exection

It cannot access the data segment, if program located in masked rom.
So we can move it to CAR/SRAM before execution.

Change-Id: If1f53a7dbd7db9643bd9aeea6567cd4fae0f310e
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/bootblock.S
2 files changed, 29 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27645/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 916e269..e36bbd6 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -28,3 +28,7 @@
 config ARCH_RAMSTAGE_RISCV
    bool
    default n
+
+config MOVE_BOOTBLOCK_TO_CAR
+	bool
+	default n
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index f92ed4b..378214c 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -37,6 +37,31 @@
    # initialize cache as ram
    call cache_as_ram

+	# It cannot access the data segment, if program located in masked rom.
+	# so we can move it to CAR/SRAM before execution.
+#if IS_ENABLED(CONFIG_MOVE_BOOTBLOCK_TO_CAR)
+_m2car:
+	la   a0, _program
+	la   a1, _eprogram
+	ld   a2, _program_execution_address
+	beq  a0, a2, _em2car
+1:
+	lb   t0, 0(a0)
+	sb   t0, 0(a2)
+	addi a0, a0, 1
+	addi a2, a2, 1
+	blt  a0, a1, 1b
+
+	ld   a0, _em2car_execution_address
+	jr   a0
+_program_execution_address:
+	.dword _program
+_em2car_execution_address:
+	.dword _em2car
+_em2car:
+
+#endif
+
    # Save the FDT pointer to memory.
    # Make mscratch vacate for exception context switching.
    csrrw a1, mscratch, zero