Change in coreboot[master]: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/1

diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index 679b101..cf1792b 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -84,6 +84,8 @@
    	},
    }"

+	register "disable_xhci_lfps_pm" = "0"
+
    device domain 0 on
    	device pci 16.0 on
    		chip drivers/i2c/hid
diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c
index 522faa9..ab75602 100644
--- a/src/mainboard/google/octopus/variants/fleex/variant.c
+++ b/src/mainboard/google/octopus/variants/fleex/variant.c
@@ -4,6 +4,7 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 #include <sar.h>
+#include <soc/intel/apollolake/chip.h>

#define MIN_LTE_SKU         4

@@ -31,3 +32,13 @@

return filename;
 }
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = NULL;
+	cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+	if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) {
+		if (is_lte_sku)
+			cfg->disable_xhci_lfps_pm = 1;
+	}
+}

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Henry Sun, Marco Chen, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46868

to look at the new patch set (#2).

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/2

[Ivy Jian (Code Review)]

Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 2: Code-Review+2

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 2:

Verified on fleex with sku id 4, bit 4-7 is 0 if set disable=1.

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 87: 	register "disable_xhci_lfps_pm" = "0"
Could we put this one with DisableComplianceMode below together since they are all related to xHCI?

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/variant.c:

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 38: 	struct soc_intel_apollolake_config *cfg = NULL;
A new line below this one at least for improving the reading.

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 41: 		if (is_lte_sku())
combine this condition into line 40?

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 2:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 87: 	register "disable_xhci_lfps_pm" = "0"
> Could we put this one with DisableComplianceMode below together since they are all related to xHCI?

Sure, fsps parameter should out of device domain. Move it here.

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/variant.c:

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 38: 	struct soc_intel_apollolake_config *cfg = NULL;
> A new line below this one at least for improving the reading.

Agree.

https://review.coreboot.org/c/coreboot/+/46868/2/src/mainboard/google/octopu... 
PS2, Line 41: 		if (is_lte_sku())
> combine this condition into line 40?

Looks like we can update it anyway.

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Henry Sun, Marco Chen, Ivy Jian, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46868

to look at the new patch set (#3).

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 15 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/3

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Henry Sun, Marco Chen, Ivy Jian, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46868

to look at the new patch set (#4).

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 15 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/4

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 4: Code-Review+1

(1 comment)

LGTM with a nit only.

https://review.coreboot.org/c/coreboot/+/46868/4/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/variant.c:

https://review.coreboot.org/c/coreboot/+/46868/4/src/mainboard/google/octopu... 
PS4, Line 41: Force update disable_xhci_lfps_pm
Force disable_xhci_lfps_pm to update

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Henry Sun, Marco Chen, Ivy Jian, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46868

to look at the new patch set (#5).

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 15 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46868/5

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46868/4/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/fleex/variant.c:

https://review.coreboot.org/c/coreboot/+/46868/4/src/mainboard/google/octopu... 
PS4, Line 41: Force update disable_xhci_lfps_pm
> Force disable_xhci_lfps_pm to update

Thanks,sorry for my poor English.

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 5:

@Marco, would you like to review again? Thank you.

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

Patch Set 5: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46868 )

Change subject: mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku
......................................................................

mb/google/octopus/var/fleex: Disable XHCI LFPS power management by sku

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Eric Lai 
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) 
Reviewed-by: Marco Chen 
---
M src/mainboard/google/octopus/variants/fleex/overridetree.cb
M src/mainboard/google/octopus/variants/fleex/variant.c
2 files changed, 15 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marco Chen: Looks good to me, approved

diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index 679b101..2fd554f 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -84,6 +84,10 @@
    	},
    }"

+	# Disable compliance mode
+	register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "0"
+
    device domain 0 on
    	device pci 16.0 on
    		chip drivers/i2c/hid
@@ -181,7 +185,4 @@
    		end
    	end	# - I2C 7
    end
-
-	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
 end
diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c
index 522faa9..5554fb3 100644
--- a/src/mainboard/google/octopus/variants/fleex/variant.c
+++ b/src/mainboard/google/octopus/variants/fleex/variant.c
@@ -4,6 +4,7 @@
 #include <baseboard/variants.h>
 #include <ec/google/chromeec/ec.h>
 #include <sar.h>
+#include <soc/intel/apollolake/chip.h>

#define MIN_LTE_SKU         4

@@ -31,3 +32,13 @@

return filename;
 }
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = NULL;
+
+	cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+	// Force disable_xhci_lfps_pm to update if it is LTE sku
+	if (cfg != NULL && is_lte_sku())
+		cfg->disable_xhci_lfps_pm = 1;
+}