Change in coreboot[master]: mb/google/octopus: Fix LPDDR4 nWR setting

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/27851

Change subject: mb/google/octopus: Fix LPDDR4 nWR setting
......................................................................

mb/google/octopus: Fix LPDDR4 nWR setting

Update nWR setting for LPDDR4 from default to 24 cycles as per spec.

BUG=b:112062440
TEST=Run memory stability test using Memtester.

Change-Id: I949d30ca9d5bb8fd876fe3c6cac7a719e771e839
Signed-off-by: Ravi Sarawadi 
---
M src/mainboard/google/octopus/variants/baseboard/memory.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27851/1

diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c
index 452d3a9..6e0fe47 100644
--- a/src/mainboard/google/octopus/variants/baseboard/memory.c
+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c
@@ -76,6 +76,7 @@
    	.ch0_dual_rank = 1,
    	.ch1_dual_rank = 1,
    	.part_num = "K4F6E304HB-MGCJ",
+		.enable_nWR_24 = 1,
    },
    /* K4F8E304HB-MGCJ - both logical channels  */
    [1] = {
@@ -83,6 +84,7 @@
    	.ch0_rank_density = LP4_8Gb_DENSITY,
    	.ch1_rank_density = LP4_8Gb_DENSITY,
    	.part_num = "K4F8E304HB-MGCJ",
+		.enable_nWR_24 = 1,
    },
    /*
     * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
@@ -97,6 +99,7 @@
    	.ch1_dual_rank = 1,
    	.part_num = "MT53B512M32D2NP",
    	.disable_periodic_retraining = 1,
+		.enable_nWR_24 = 1,
    },
    /* MT53B256M32D1NP-062 WT:C - both logical channels */
    [3] = {
@@ -105,6 +108,7 @@
    	.ch1_rank_density = LP4_8Gb_DENSITY,
    	.part_num = "MT53B256M32D1NP",
    	.disable_periodic_retraining = 1,
+		.enable_nWR_24 = 1,
    },
    /*
     * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
@@ -118,6 +122,7 @@
    	.ch0_dual_rank = 1,
    	.ch1_dual_rank = 1,
    	.part_num = "H9HCNNNBPUMLHR",
+		.enable_nWR_24 = 1,
    },
    /* H9HCNNN8KUMLHR-NLE - both logical channels */
    [5] = {
@@ -125,6 +130,7 @@
    	.ch0_rank_density = LP4_8Gb_DENSITY,
    	.ch1_rank_density = LP4_8Gb_DENSITY,
    	.part_num = "H9HCNNN8KUMLHR",
+		.enable_nWR_24 = 1,
    },
    /* K4F6E3S4HM-MGCJ - both logical channels */
    [6] = {
@@ -132,6 +138,7 @@
    	.ch0_rank_density = LP4_16Gb_DENSITY,
    	.ch1_rank_density = LP4_16Gb_DENSITY,
    	.part_num = "K4F6E3S4HM-MGCJ",
+		.enable_nWR_24 = 1,
    },
    /* MT53E512M32D2NP-046 - both logical channels */
    [7] = {
@@ -139,6 +146,7 @@
    	.ch0_rank_density = LP4_16Gb_DENSITY,
    	.ch1_rank_density = LP4_16Gb_DENSITY,
    	.part_num = "MT53E512M32D2NP",
+		.enable_nWR_24 = 1,
    },
 };