[S] Change in coreboot[main]: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81042?usp=email )

(

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
......................................................................

soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms

NUMA will be supported by SPR and future generations.

TEST=intel/archercity CRB

Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26
Signed-off-by: Shuo Liu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.mk
R src/soc/intel/xeon_sp/numa.c
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/Makefile.mk
5 files changed, 6 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 59335a1..52aaec17 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -106,4 +106,7 @@
 config HAVE_IOAT_DOMAINS
    bool

+config SOC_INTEL_HAS_CXL
+	bool
+
 endif ## SOC_INTEL_XEON_SP
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk
index a732c78..5891544 100644
--- a/src/soc/intel/xeon_sp/Makefile.mk
+++ b/src/soc/intel/xeon_sp/Makefile.mk
@@ -13,7 +13,7 @@
 ramstage-y += memmap.c pch.c lockdown.c finalize.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
-ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c
+ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 smm-y += smihandler.c pmutil.c
 postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/numa.c
similarity index 100%
rename from src/soc/intel/xeon_sp/spr/numa.c
rename to src/soc/intel/xeon_sp/numa.c
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index acc5e4a..3c3c45a 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -15,6 +15,7 @@
    select HAVE_IOAT_DOMAINS
    select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
    select UDK_202005_BINDING
+	select SOC_INTEL_HAS_CXL
    help
      Intel Sapphire Rapids-SP support

@@ -114,9 +115,6 @@
 config SOC_INTEL_HAS_NCMEM
    def_bool y

-config SOC_INTEL_HAS_CXL
-	def_bool y
-
 config SOC_INTEL_PCIE_64BIT_ALLOC
    def_bool y

diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index 659e366..163b5ea 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -12,7 +12,7 @@
 romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c

-ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.c
+ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c
 ramstage-y += crashlog.c ioat.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c