Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37140 )

Change subject: sb/intel/ibexpeak: Use common AHCI
......................................................................

sb/intel/ibexpeak: Use common AHCI

Untested.

Change-Id: I772e69fe4400d921bea12806a0ab159b7cf5fbe1
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/sata.c
2 files changed, 4 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37140/1

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index f9723fb..c923714 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -26,6 +26,7 @@
    select USE_WATCHDOG_ON_BOOT
    select PCIEXP_ASPM
    select PCIEXP_COMMON_CLOCK
+	select SOUTHBRIDGE_INTEL_COMMON_AHCI
    select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
    select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
    select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 2d9412a..aa39a54 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -24,6 +24,7 @@
 #include <pc80/mc146818rtc.h>
 #include <acpi/sata.h>
 #include <types.h>
+#include <southbridge/intel/common/ahci.h>

#include "chip.h"
 #include "pch.h"
@@ -68,8 +69,6 @@

if (sata_mode == 0) {
    	/* AHCI */
-		u32 *abar;
-
    	printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");

/* Set Interrupt Line */
@@ -104,31 +103,8 @@
    	pci_write_config32(dev, 0x98, 0x00590200);

/* Initialize AHCI memory-mapped space */
-		abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-		/* CAP (HBA Capabilities) : enable power management */
-		reg32 = read32(abar + 0x00);
-		reg32 |= 0x0c006000;	// set PSC+SSC+SALP+SSS
-		reg32 &= ~0x00020060;	// clear SXS+EMS+PMS
-		/* Set ISS, if available */
-		if (config->sata_interface_speed_support) {
-			reg32 &= ~0x00f00000;
-			reg32 |= (config->sata_interface_speed_support & 0x03)
-			    << 20;
-		}
-		write32(abar + 0x00, reg32);
-		/* PI (Ports implemented) */
-		write32(abar + 0x03, config->sata_port_map);
-		(void)read32(abar + 0x03);	/* Read back 1 */
-		(void)read32(abar + 0x03);	/* Read back 2 */
-		/* CAP2 (HBA Capabilities Extended) */
-		reg32 = read32(abar + 0x09);
-		reg32 &= ~0x00000002;
-		write32(abar + 0x09, reg32);
-		/* VSP (Vendor Specific Register */
-		reg32 = read32(abar + 0x28);
-		reg32 &= ~0x00000005;
-		write32(abar + 0x28, reg32);
+		sb_ahci_init(dev, config->sata_port_map, false, false,
+			     config->sata_interface_speed_support, false, 5);
    } else {
    	/* IDE */
    	printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37140 )

Change subject: sb/intel/ibexpeak: Use common AHCI
......................................................................

Patch Set 3:

Tested on Lenovo T410, still boots from SATA.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37140 )

Change subject: sb/intel/ibexpeak: Use common AHCI
......................................................................

Patch Set 3: Code-Review+1

I can test this on a half-ported HP 630 laptop, but it might be better to test with the T410 as it is already in the tree

[S] Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37140?usp=email )

Change subject: sb/intel/ibexpeak: Use common AHCI
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.