Attention is currently required from: Sajida Bhanu. Hello Sajida Bhanu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/57312
to review the following change.
Change subject: mainboard/google/herobrine: Increase the ROM size ......................................................................
mainboard/google/herobrine: Increase the ROM size
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update coreboot ROM size to match with SPI NOR size.
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up.
Signed-off-by: Shaik Sajida Bhanu sbhanu@codeaurora.org Change-Id: Ifb41dc4bfbc43be7f2a53c8a8ebfd5f490f0de5f --- M src/drivers/spi/spi_flash.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/57312/1
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f3cecd5..47de069 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -506,6 +506,7 @@ mode_string = " (Dual I/O mode)"; else if (flash->flags.dual_output && spi.ctrlr->xfer_dual) mode_string = " (Dual Output mode)"; + printk(BIOS_INFO, "SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n", flash->vendor, flash->model, flash->sector_size, flash->size, mode_string); diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index e963f4c..a2e10a0 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -5,7 +5,8 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_65536 if BOARD_GOOGLE_PIGLIN + select BOARD_ROMSIZE_KB_8192 if !BOARD_GOOGLE_PIGLIN select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC if !BOARD_GOOGLE_SENOR select EC_GOOGLE_CHROMEEC_RTC if !BOARD_GOOGLE_SENOR