Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable PCIE X1, X4 and X16 slot

[Kin Wai Ng (Code Review)]

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/25238

to review the following change.

Change subject: mainboard/intel/coffeelake_rvp: Enable PCIE X1, X4 and X16 slot
......................................................................

mainboard/intel/coffeelake_rvp: Enable PCIE X1, X4 and X16 slot

Refer schematic:
GPP_B_8_SRCCLKREQB_3
GPP_B_9_SRCCLKREQB_4
GPP_H_2_SRCCLKREQB_8

Change-Id: I95bb69d27b595669e4790fb73de60e724f49dc83
Signed-off-by: Ng Kin Wai 
---
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
1 file changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25238/1

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index f84400d..a6d9a6e 100755
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -62,13 +62,20 @@
    register "PcieRpEnable[11]" = "1"
    register "PcieRpEnable[12]" = "1"
    register "PcieRpEnable[13]" = "1"
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpEnable[15]" = "1"
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpEnable[21]" = "1"
+	register "PcieRpEnable[22]" = "1"
+	register "PcieRpEnable[23]" = "1"

register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
    register "PcieClkSrcUsage[1]" = "8"
    register "PcieClkSrcUsage[2]" = "0xff" #NOT_USE
-	register "PcieClkSrcUsage[3]" = "14"
-	register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "0x6"
+	register "PcieClkSrcUsage[4]" = "0x18"
    register "PcieClkSrcUsage[5]" = "1"
+	register "PcieClkSrcUsage[8]" = "0x40"
    register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"

register "PcieClkSrcClkReq[0]" = "0"
@@ -77,6 +84,7 @@
    register "PcieClkSrcClkReq[3]" = "3"
    register "PcieClkSrcClkReq[4]" = "4"
    register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[8]" = "8"
    register "PcieClkSrcClkReq[9]" = "9"

# Enable "Intel Speed Shift Technology"