Change in coreboot[master]: soc/intel/alderlake: Enable VT-d

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Ronak Kanabar, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 )

Change subject: soc/intel/alderlake: Enable VT-d
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Patch Set 5:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/51849/comment/4c13e225_975080d2 
PS3, Line 198: /* Disable VT-d support for pre-QS platform */
> Lets first enable the VTD UPD alone and take FSP debug log to see what all FSP is doing. […]

@Furquan, we verified the working on the early silicon as well and hence skipped the check like in tigerlake and enabled by default.