Change in coreboot[master]: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""

This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba.

Reason for revert: Resource allocator is split into old(v3) and
new(v4). So, this change to enable hotplug resource allocator for
volteer can land back.

BUG=b:149186922

Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/volteer/Kconfig
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41468/1

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index de77633..6875963 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -15,6 +15,7 @@
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_SPI_TPM_CR50
    select MAINBOARD_HAS_TPM2
+	select PCIEXP_HOTPLUG
    select SOC_INTEL_TIGERLAKE

if BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -66,6 +67,20 @@
    int
    default 8

+# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569)
+# Revision 0.7.6 Section 7.2.5.1.5
+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000  # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c000000 # 448 MiB
+
 config TPM_TIS_ACPI_INTERRUPT
    int
    default 21  # GPE0_DW0_21 (GPP_C21)

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 1:

it will display SeaBIOS but not boot
maybe i'm doing something wrong
I'll try again

here is the log as I have it :p 
but maybe I'm wrong 
https://pastebin.com/SKk9qFvR

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 1:
> Patch Set 1:
>
> it will display SeaBIOS but not boot
> maybe i'm doing something wrong
> I'll try again
>
> here is the log as I have it :p 
> but maybe I'm wrong 
> https://pastebin.com/SKk9qFvR

The logs that you have are with the old(v3) resource allocator. Are you seeing problems with that too? Also, what mainboard is this?

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 1:
> Patch Set 1:
> > Patch Set 1:
> >
> > it will display SeaBIOS but not boot
> > maybe i'm doing something wrong
> > I'll try again
> >
> > here is the log as I have it :p 
> > but maybe I'm wrong 
> > https://pastebin.com/SKk9qFvR
>
> The logs that you have are with the old(v3) resource allocator. Are you seeing problems with that too? Also, what mainboard is this?

it is an i945GC + ICH7 based board https://review.coreboot.org/c/coreboot/+/25509

for current test, what I did is:" git fetch "ssh://[e-mail]:29418/coreboot" refs/changes/68/41468/1 && git checkout FETCH_HEAD" then I've rebased on it

I've checked, looks like there is no mistake.

I'll give a shot again to the parent patchs maybe I did a mistake

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 1:
> Patch Set 1:
> > Patch Set 1:
> > > Patch Set 1:
> > >
> > > it will display SeaBIOS but not boot
> > > maybe i'm doing something wrong
> > > I'll try again
> > >
> > > here is the log as I have it :p 
> > > but maybe I'm wrong 
> > > https://pastebin.com/SKk9qFvR
> >
> > The logs that you have are with the old(v3) resource allocator. Are you seeing problems with that too? Also, what mainboard is this?
>
> it is an i945GC + ICH7 based board https://review.coreboot.org/c/coreboot/+/25509
>
> for current test, what I did is:" git fetch "ssh://[e-mail]:29418/coreboot" refs/changes/68/41468/1 && git checkout FETCH_HEAD" then I've rebased on it
>
> I've checked, looks like there is no mistake.
>
> I'll give a shot again to the parent patchs maybe I did a mistake

Thanks for the logs and the details Elyes! I don't think you are doing anything wrong. I see some differences with old and new allocator in the I/O allocation. It looks like we have some problem in other parts of the tree w.r.t. resource reporting. I will have to study the logs some more to get a better understanding of what might be going on. I can give you a patch probably in a day to test out more. Thanks again for trying out the changes.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 1: Code-Review+1

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41468

to look at the new patch set (#3).

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""

This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba.

Reason for revert: Resource allocator is split into old(v3) and
new(v4). So, this change to enable hotplug resource allocator for
volteer can land back.

BUG=b:149186922

Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/volteer/Kconfig
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41468/3

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 3:
> Patch Set 1:
> > Patch Set 1:
> > > Patch Set 1:
> > > > Patch Set 1:
> > > >
> > > > it will display SeaBIOS but not boot
> > > > maybe i'm doing something wrong
> > > > I'll try again
> > > >
> > > > here is the log as I have it :p 
> > > > but maybe I'm wrong 
> > > > https://pastebin.com/SKk9qFvR
> > >
> > > The logs that you have are with the old(v3) resource allocator. Are you seeing problems with that too? Also, what mainboard is this?
> >
> > it is an i945GC + ICH7 based board https://review.coreboot.org/c/coreboot/+/25509
> >
> > for current test, what I did is:" git fetch "ssh://[e-mail]:29418/coreboot" refs/changes/68/41468/1 && git checkout FETCH_HEAD" then I've rebased on it
> >
> > I've checked, looks like there is no mistake.
> >
> > I'll give a shot again to the parent patchs maybe I did a mistake
>
> Thanks for the logs and the details Elyes! I don't think you are doing anything wrong. I see some differences with old and new allocator in the I/O allocation. It looks like we have some problem in other parts of the tree w.r.t. resource reporting. I will have to study the logs some more to get a better understanding of what might be going on. I can give you a patch probably in a day to test out more. Thanks again for trying out the changes.

Hi Elyes, I have uploaded a new patchset that should solve the problem that you are seeing with the new resource allocator. Let me know how that goes for you. Thanks!

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 1:
> > > Patch Set 1:
> > > > Patch Set 1:
> > > > > Patch Set 1:
> > > > >
> > > > > it will display SeaBIOS but not boot
> > > > > maybe i'm doing something wrong
> > > > > I'll try again
> > > > >
> > > > > here is the log as I have it :p 
> > > > > but maybe I'm wrong 
> > > > > https://pastebin.com/SKk9qFvR
> > > >
> > > > The logs that you have are with the old(v3) resource allocator. Are you seeing problems with that too? Also, what mainboard is this?
> > >
> > > it is an i945GC + ICH7 based board https://review.coreboot.org/c/coreboot/+/25509
> > >
> > > for current test, what I did is:" git fetch "ssh://[e-mail]:29418/coreboot" refs/changes/68/41468/1 && git checkout FETCH_HEAD" then I've rebased on it
> > >
> > > I've checked, looks like there is no mistake.
> > >
> > > I'll give a shot again to the parent patchs maybe I did a mistake
> >
> > Thanks for the logs and the details Elyes! I don't think you are doing anything wrong. I see some differences with old and new allocator in the I/O allocation. It looks like we have some problem in other parts of the tree w.r.t. resource reporting. I will have to study the logs some more to get a better understanding of what might be going on. I can give you a patch probably in a day to test out more. Thanks again for trying out the changes.
>
> Hi Elyes, I have uploaded a new patchset that should solve the problem that you are seeing with the new resource allocator. Let me know how that goes for you. Thanks!

Hi Furquan,
Thank you.
Please see https://review.coreboot.org/c/coreboot/+/25509/41 
you will find all the logs of yesterday and the those of today

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Patch Set 8: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41468 )

Change subject: Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
......................................................................

Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""

This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba.

Reason for revert: Resource allocator is split into old(v3) and
new(v4). So, this change to enable hotplug resource allocator for
volteer can land back.

BUG=b:149186922

Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
Reviewed-by: Angel Pons 
---
M src/mainboard/google/volteer/Kconfig
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 9c7292f..7ed685a 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -19,6 +19,7 @@
    select MAINBOARD_HAS_CHROMEOS
    select MAINBOARD_HAS_SPI_TPM_CR50
    select MAINBOARD_HAS_TPM2
+	select PCIEXP_HOTPLUG
    select SOC_INTEL_TIGERLAKE

if BOARD_GOOGLE_BASEBOARD_VOLTEER
@@ -72,6 +73,20 @@
    int
    default 8

+# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569)
+# Revision 0.7.6 Section 7.2.5.1.5
+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000  # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c000000 # 448 MiB
+
 config TPM_TIS_ACPI_INTERRUPT
    int
    default 21  # GPE0_DW0_21 (GPP_C21)