Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Hello Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/55685
to review the following change.
Change subject: mb/lenovo/t440p: Drop redundancy in devtree comments ......................................................................
mb/lenovo/t440p: Drop redundancy in devtree comments
Remove some redundant parts of devicetree comments. This used to happen when using autoport, but has been fixed at some point.
Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical.
Change-Id: Ie24b5430c7771c9ce4dda6c9a10d70ee9000df7c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/lenovo/t440p/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/55685/1
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 09821be..a1f1ac7 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -22,10 +22,10 @@ device domain 0 on subsystemid 0x17aa 0x220e inherit
- device pci 00.0 on end # Host bridge Host bridge + device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller - device pci 03.0 on end # Mini-HD audio Audio controller + device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH register "gen1_dec" = "0x007c1601" @@ -54,7 +54,7 @@ device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01"
-
Angel Pons (Code Review)