[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size

[Michał Żygowski (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Nico Huber.

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email )

Change subject: device/pciexp_device.c: Fix setting Max Payload Size
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Patch Set 10:

(1 comment)

File src/device/pciexp_device.c:

https://review.coreboot.org/c/coreboot/+/77338/comment/6fb86eb0_8d0770bb :
PS10, Line 645: 	pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap);
pciexp_tune_dev is called for all children on the bus. pciexp_scan_bus is the scan bus op for root ports, downstream and upstream devices, so it should be covered I think.
> Also, PCIe specifications describes special treatment of ARI devices, i.e. only Function 0 of such device should be considered.

For devices not being Root Bridges?