Change in coreboot[master]: mb/google/mancomb: Enable AP <-> H1 communication

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52175 )

Change subject: mb/google/mancomb: Enable AP <-> H1 communication
......................................................................

mb/google/mancomb: Enable AP <-> H1 communication

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai 
Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175
Tested-by: build bot (Jenkins) 
Reviewed-by: Mathew King 
---
M src/mainboard/google/mancomb/Kconfig
M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
M src/mainboard/google/mancomb/variants/baseboard/gpio.c
3 files changed, 24 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig
index 85a50b3..5851e5c 100644
--- a/src/mainboard/google/mancomb/Kconfig
+++ b/src/mainboard/google/mancomb/Kconfig
@@ -20,6 +20,8 @@
    select ELOG_GSMI
    select HAVE_ACPI_RESUME
    select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select MAINBOARD_HAS_TPM2
    select SOC_AMD_CEZANNE
    select SOC_AMD_COMMON_BLOCK_USE_ESPI

@@ -49,6 +51,14 @@
    help
      TODO: might need to be adapted for better placement of files in cbfs

+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x03
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 config VARIANT_DIR
    string
    default "mancomb" if BOARD_GOOGLE_MANCOMB
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index 533e2b4..0a604a3 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -121,5 +121,13 @@
    			device pnp 0c09.0 on end
    		end
    	end
+		device ref i2c_3 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "desc" = ""Cr50 TPM""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)"
+				device i2c 50 on end
+			end
+		end
    end # domain
 end	# chip soc/amd/cezanne
diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
index bcca693c..cd86f9c 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c
+++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
@@ -163,6 +163,12 @@

/* Early GPIO configuration */
 static const struct soc_amd_gpio early_gpio_table[] = {
+	/* GSC_SOC_INT_L */
+	PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+	/* I2C3_SCL */
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+	/* I2C3_SDA */
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
    /* ESPI1_DATA0 */
    PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
    /* ESPI1_DATA1 */