Change in coreboot[master]: trogdor: Add third RAM_CODE pin

[Julius Werner (Code Review)]

Hello Philip Chen, mturney mturney,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40352

to review the following change.

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

trogdor: Add third RAM_CODE pin

We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.

Signed-off-by: Julius Werner 
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
---
M src/mainboard/google/trogdor/boardid.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/40352/1

diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c
index 9d92988..1b3a269 100644
--- a/src/mainboard/google/trogdor/boardid.c
+++ b/src/mainboard/google/trogdor/boardid.c
@@ -20,7 +20,7 @@
 {
    static uint32_t id = UNDEFINED_STRAPPING_ID;

-	const gpio_t pins[] = {[1] = GPIO(91), [0] = GPIO(29)};
+	const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(91), [0] = GPIO(29)};

if (id == UNDEFINED_STRAPPING_ID)
    	id = gpio_base2_value(pins, ARRAY_SIZE(pins));

[Philip Chen (Code Review)]

Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

Patch Set 1: Code-Review+1

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

Patch Set 1:

Can you just +2 please? It's a trivial change and nobody else with +2 rights works on this board...

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

Patch Set 1: Code-Review+2

[Philip Chen (Code Review)]

Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

Patch Set 1: Code-Review+2

Sure, I was hoping someone from QCOM can take a look before I give it a +2.

[Julius Werner (Code Review)]

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

trogdor: Add third RAM_CODE pin

We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.

Signed-off-by: Julius Werner 
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
Reviewed-by: Philip Chen 
---
M src/mainboard/google/trogdor/boardid.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Philip Chen: Looks good to me, approved

diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c
index 9d92988..1b3a269 100644
--- a/src/mainboard/google/trogdor/boardid.c
+++ b/src/mainboard/google/trogdor/boardid.c
@@ -20,7 +20,7 @@
 {
    static uint32_t id = UNDEFINED_STRAPPING_ID;

-	const gpio_t pins[] = {[1] = GPIO(91), [0] = GPIO(29)};
+	const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(91), [0] = GPIO(29)};

if (id == UNDEFINED_STRAPPING_ID)
    	id = gpio_base2_value(pins, ARRAY_SIZE(pins));

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40352 )

Change subject: trogdor: Add third RAM_CODE pin
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2319
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2318
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2317

Please note: This test is under development and might not be accurate at all!