jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
There are some extra data transfer in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calc by video timing.
So dsi driver reduces the hbp and hfp to keep the line time.
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c 1 file changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/1
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb..66bc6b6 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -73,30 +73,28 @@
static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) { - u32 cycle_time, ui; - - ui = 1000 / data_rate + 0x01; - cycle_time = 8000 / data_rate + 0x01; + u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
memset(phy_timing, 0, sizeof(*phy_timing));
- phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); + phy_timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; + phy_timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; + phy_timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 - + phy_timing->da_hs_prepare + 1; + phy_timing->da_hs_trail = phy_timing->da_hs_prepare + 1;
- phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; + phy_timing->ta_go = 4 * phy_timing->lpx - 2; + phy_timing->ta_sure = phy_timing->lpx + 2; + phy_timing->ta_get = 4 * phy_timing->lpx; + phy_timing->da_hs_exit = 2 * phy_timing->lpx + 1;
phy_timing->da_hs_sync = 1; - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + phy_timing->clk_hs_zero = phy_timing->clk_hs_trail * 4; + phy_timing->clk_hs_trail = phy_timing->clk_hs_prepare;
- phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + phy_timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); + phy_timing->clk_hs_post = phy_timing->clk_hs_prepare + 8; + phy_timing->clk_hs_exit = 2 * phy_timing->clk_hs_trail;
/* Allow board-specific tuning. */ mtk_dsi_override_phy_timing(phy_timing); @@ -200,12 +198,12 @@ hspw = edid->mode.hspw;
hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) - * bytes_per_pixel - 10; + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel;
data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
u32 delta = 12; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) @@ -214,11 +212,13 @@ u32 d_phy = phy_timing->d_phy; if (d_phy == 0) d_phy = data_phy_cycles * lanes + delta; - if (hfp_byte > d_phy) - hfp_byte -= d_phy; - else + if ((hfp_byte + hbp_byte) > d_phy) { + hfp_byte -= (d_phy * hfp_byte) / (hfp_byte + hbp_byte); + hbp_byte -= (d_phy * hbp_byte) / (hfp_byte + hbp_byte); + } else { printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " "and the panel may not work properly.\n"); + }
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@9 PS1, Line 9: transfer tranfers
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@12 PS1, Line 12: calc calculated
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@14 PS1, Line 14: So dsi driver reduces the hbp and hfp to keep the line time. Please give exact time values.
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... PS1, Line 74: int data_rate That argument doesn’t seem to be used anymore.
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... PS1, Line 201: * bytes_per_pixel - 10; Formatting shouldn’t be changed.
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38400
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
There are some extra data tranfers in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calculated by video timing.
So dsi driver reduces the hbp and hfp to keep the line time. hbp = hbp - phy_extra * hbp / (hbp + hfp) hfp = hfp - phy_extra * hfp / (hbp + hfp)
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c 1 file changed, 22 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 2:
(8 comments)
Please test and verify this on real kukui units.
https://review.coreboot.org/c/coreboot/+/38400/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38400/2//COMMIT_MSG@17 PS2, Line 17: Add
BUG=b:144824303 BRANCH=kukui TEST=Boots and sees firmware screen on krane and jacuzzi
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 78: (8 * 1000) 8000
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 79: 4 * 1000 4000
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 80: 10 * 1000 10000
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 85: + 2 no need to do / 2?
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 86: 4 * phy_timing->lpx; Are you sure the new value will still work for both MIPI (krane) and EDP (jacuzzi)?
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 93: (8 * 1000) 8000
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 213: hfp_byte + hbp_byte) this is repeated 3 times so let's make a variable for it, for example:
u32 total_bytes = hfp_byte + hbp_byte;
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 78: (8 * 1000)
8000
Why not (8 * KHz)?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 74: data_rate to make it easier sync with kernel code, you can rename the params :
data_rate => data_rate_mhz phy_timing => timing
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 90: clk_hs_trail hs_trail is not available (set in next line).
You probably want to re-order by what kernel patch did ( https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1... )
Hung-Te Lin has uploaded a new patch set (#3) to the change originally created by jitao shi. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
There are some extra data tranfers in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calculated by video timing.
So dsi driver reduces the hbp and hfp to keep the line time:
hbp = hbp - phy_extra * hbp / (hbp + hfp) hfp = hfp - phy_extra * hfp / (hbp + hfp)
Also refactored to sync with DSI driver in kernel upstream.
BUG=b:144824303 BRANCH=kukui TEST=Boots and sees firmware screen on krane and jacuzzi
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c 1 file changed, 41 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/3
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 3:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@9 PS1, Line 9: transfer
tranfers
Done
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@12 PS1, Line 12: calc
calculated
Done
https://review.coreboot.org/c/coreboot/+/38400/1//COMMIT_MSG@14 PS1, Line 14: So dsi driver reduces the hbp and hfp to keep the line time.
Please give exact time values.
Done
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... PS1, Line 74: int data_rate
That argument doesn’t seem to be used anymore.
Done
https://review.coreboot.org/c/coreboot/+/38400/1/src/soc/mediatek/common/dsi... PS1, Line 201: * bytes_per_pixel - 10;
Formatting shouldn’t be changed.
Done
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 74: data_rate
to make it easier sync with kernel code, you can rename the params : […]
Ack
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 78: (8 * 1000)
Why not (8 * KHz)?
Seems like the phy timing config is identical to kernel implementation so it's easier to use same name and code from there - that's why this is 1000 instead of KHz.
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 79: 4 * 1000
4000
Ack
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 80: 10 * 1000
10000
Ack
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 85: + 2
no need to do / 2?
Ack
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 90: clk_hs_trail
hs_trail is not available (set in next line). […]
Ack
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 93: (8 * 1000)
8000
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Let's wait until we have a fix for b/149051882.
https://review.coreboot.org/c/coreboot/+/38400/3/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/3/src/soc/mediatek/common/dsi... PS3, Line 214: hfp_byte -= (d_phy * hfp_byte) / (hfp_byte + hbp_byte); : hbp_byte -= (d_phy * hbp_byte) / (hfp_byte + hbp_byte); This is different from kernel. See CL:2053515.
Yu-Ping Wu has uploaded a new patch set (#4) to the change originally created by jitao shi. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek: dsi: reduce the hbp and hfp for phy timing
There are some extra data tranfers in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calculated by video timing.
So dsi driver reduces the hbp and hfp to keep the line time:
hbp = hbp - phy_extra * hbp / (hbp + hfp) hfp = hfp - phy_extra * hfp / (hbp + hfp)
Also refactored to sync with DSI driver in kernel upstream.
BUG=b:144824303 BRANCH=kukui TEST=Boots and sees firmware screen on krane and jacuzzi
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c 1 file changed, 41 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/4
Yu-Ping Wu has uploaded a new patch set (#5) to the change originally created by jitao shi. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek: dsi: reduce the hbp and hfp for phy timing
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen.
To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442.
Also rename 'phy_timing' to 'timing' to sync with kernel upstream.
Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed.
BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu yupingso@google.com --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c 2 files changed, 49 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/5
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38400/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38400/2//COMMIT_MSG@17 PS2, Line 17:
Add […]
Done
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 213: hfp_byte + hbp_byte)
this is repeated 3 times so let's make a variable for it, for example: […]
I think writing it this way is easier to read.
https://review.coreboot.org/c/coreboot/+/38400/3/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/3/src/soc/mediatek/common/dsi... PS3, Line 214: hfp_byte -= (d_phy * hfp_byte) / (hfp_byte + hbp_byte); : hbp_byte -= (d_phy * hbp_byte) / (hfp_byte + hbp_byte);
This is different from kernel. See CL:2053515.
Done
Yu-Ping Wu has uploaded a new patch set (#6) to the change originally created by jitao shi. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek: dsi: reduce the hbp and hfp for phy timing
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen.
To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442.
Also rename 'phy_timing' to 'timing' to sync with kernel upstream.
Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed.
BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu yupingso@google.com --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c 2 files changed, 49 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/6
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 86: 4 * phy_timing->lpx;
Are you sure the new value will still work for both MIPI (krane) and EDP (jacuzzi)?
Tested on krane.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/38400/2/src/soc/mediatek/common/dsi... PS2, Line 213: hfp_byte + hbp_byte)
I think writing it this way is easier to read.
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38400 )
Change subject: soc/mediatek: dsi: reduce the hbp and hfp for phy timing ......................................................................
soc/mediatek: dsi: reduce the hbp and hfp for phy timing
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen.
To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442.
Also rename 'phy_timing' to 'timing' to sync with kernel upstream.
Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed.
BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels
Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu yupingso@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c 2 files changed, 49 insertions(+), 45 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 293cc1c..9387a83b 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -273,7 +273,7 @@ return 1; }
- *m = (unsigned long long)pixelclock * 599 / 600; + *m = pixelclock; *n = XTAL_FRQ / post_divider; *pd = post_divider;
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 9222cb0..be99fe8 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -74,47 +74,43 @@ /* Do nothing. */ }
-static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *phy_timing) +static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *timing) { - u32 cycle_time, ui; + u32 timcon0, timcon1, timcon2, timcon3; u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
- ui = 1000 / data_rate_mhz + 0x01; - cycle_time = 8000 / data_rate_mhz + 0x01; + memset(timing, 0, sizeof(*timing));
- memset(phy_timing, 0, sizeof(*phy_timing)); + timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; + timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; + timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - + timing->da_hs_prepare; + timing->da_hs_trail = timing->da_hs_prepare + 1;
- phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); + timing->ta_go = 4 * timing->lpx - 2; + timing->ta_sure = timing->lpx + 2; + timing->ta_get = 4 * timing->lpx; + timing->da_hs_exit = 2 * timing->lpx + 1;
- phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; + timing->da_hs_sync = 1;
- phy_timing->da_hs_sync = 1; - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; - - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); + timing->clk_hs_post = timing->clk_hs_prepare + 8; + timing->clk_hs_trail = timing->clk_hs_prepare; + timing->clk_hs_zero = timing->clk_hs_trail * 4; + timing->clk_hs_exit = 2 * timing->clk_hs_trail;
/* Allow board-specific tuning. */ - mtk_dsi_override_phy_timing(phy_timing); + mtk_dsi_override_phy_timing(timing);
- u32 timcon0, timcon1, timcon2, timcon3; - - timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | - phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; - timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | - phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; - timcon2 = phy_timing->da_hs_sync << 8 | phy_timing->clk_hs_zero << 16 | - phy_timing->clk_hs_trail << 24; - timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | - phy_timing->clk_hs_exit << 16; + timcon0 = timing->lpx | timing->da_hs_prepare << 8 | + timing->da_hs_zero << 16 | timing->da_hs_trail << 24; + timcon1 = timing->ta_go | timing->ta_sure << 8 | + timing->ta_get << 16 | timing->da_hs_exit << 24; + timcon2 = timing->da_hs_sync << 8 | timing->clk_hs_zero << 16 | + timing->clk_hs_trail << 24; + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | + timing->clk_hs_exit << 16;
write32(&dsi0->dsi_phy_timecon0, timcon0); write32(&dsi0->dsi_phy_timecon1, timcon1); @@ -180,6 +176,8 @@ const struct mtk_phy_timing *phy_timing) { u32 hsync_active_byte; + u32 hbp; + u32 hfp; u32 hbp_byte; u32 hfp_byte; u32 vbp_byte; @@ -199,17 +197,20 @@ write32(&dsi0->dsi_vfp_nl, vfp_byte); write32(&dsi0->dsi_vact_nl, edid->mode.va);
- unsigned int hspw = 0; - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hspw = edid->mode.hspw; - - hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) - * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; - hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; + + hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder; + hfp = edid->mode.hso - edid->mode.hborder; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = hbp * bytes_per_pixel - 10; + else + hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10; + hfp_byte = hfp * bytes_per_pixel;
data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
u32 delta = 12; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) @@ -218,11 +219,14 @@ u32 d_phy = phy_timing->d_phy; if (d_phy == 0) d_phy = data_phy_cycles * lanes + delta; - if (hfp_byte > d_phy) - hfp_byte -= d_phy; - else - printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " - "and the panel may not work properly.\n"); + + if ((hfp + hbp) * bytes_per_pixel > d_phy) { + hfp_byte -= d_phy * hfp / (hfp + hbp); + hbp_byte -= d_phy * hbp / (hfp + hbp); + } else { + printk(BIOS_ERR, "HFP plus HBP is not greater than d_phy, " + "the panel may not work properly.\n"); + }
write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte);
-
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